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<title>AT-0000LI02/rtl/uncore/clkgen.sv, branch main</title>
<subtitle>The AT-0000LI02 automotive SoC.
</subtitle>
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<updated>2026-09-25T22:39:40Z</updated>
<entry>
<title>uncore: clkgen: Add 300 MHz phased locked loop</title>
<updated>2026-09-25T22:39:40Z</updated>
<author>
<name>Ian M.</name>
<email>ian@aptel.org</email>
</author>
<published>2026-09-25T22:39:40Z</published>
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<content type='text'>
Signed-off-by: Ian M. &lt;ian@aptel.org&gt;
</content>
</entry>
<entry>
<title>initial commit</title>
<updated>2026-09-25T22:17:07Z</updated>
<author>
<name>Ian M.</name>
<email>ian@aptel.org</email>
</author>
<published>2026-09-25T22:17:07Z</published>
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Signed-off-by: Ian M. &lt;ian@aptel.org&gt;
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