board: xc7a35tcpg236a: Update board files

Signed-off-by: Ian M. <ian@aptel.org>
author: Ian M. <ian@aptel.org> 2026-09-25 22:39:24 +0000
committer: Ian M. <ian@aptel.org> 2026-09-25 22:39:24 +0000
commit: 939ab54f84f2605df494872cde6f1030ea211436 (patch)
tree: 5b275002b42d9ceb62b6fbba1fd8f4057eb82b74 /board
parent: f62fb60529f1f7bd9132513d0b39b715d9bdcd25 (diff)
164 files changed, 18808 insertions, 5041 deletions
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/.gitignore b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/.gitignore
new file mode 100644
index 0000000..a92e810
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/.gitignore
@@ -0,0 +1 @@
+*.runs
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/d2fa91287cc072e8.xci b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/d2fa91287cc072e8.xci
new file mode 100644
index 0000000..60ce73c
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/d2fa91287cc072e8.xci
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>ipcache</spirit:library>
+  <spirit:name>d2fa91287cc072e8</spirit:name>
+  <spirit:version>0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>gpll</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">111.879</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">105.461</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">300.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">gpll</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">cpg236</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">e6a05ff8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">d2fa91287cc072e8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">gpll</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 6500266 $</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">bff9322a</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">31</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2026.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll.dcp
new file mode 100644
index 0000000..f213a10
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll.dcp
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.v
new file mode 100755
index 0000000..6c74dbd
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.v
@@ -0,0 +1,220 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+// Date        : Fri Sep 25 22:25:05 2026
+// Host        : IRON-B running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gpll_sim_netlist.v
+// Design      : gpll
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a35tcpg236-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire clk_out1;
+  wire locked;
+  wire reset;
+
+  decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .clk_out1(clk_out1),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_gpll;
+  wire clk_out1;
+  wire clk_out1_gpll;
+  wire clkfbout_buf_gpll;
+  wire clkfbout_gpll;
+  wire locked;
+  wire reset;
+  wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_gpll),
+        .O(clkfbout_buf_gpll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_gpll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_out1_gpll),
+        .O(clk_out1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(9),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(10.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(3),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_gpll),
+        .CLKFBOUT(clkfbout_gpll),
+        .CLKIN1(clk_in1_gpll),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(clk_out1_gpll),
+        .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+        .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.vhdl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.vhdl
new file mode 100755
index 0000000..1f2358d
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_sim_netlist.vhdl
@@ -0,0 +1,151 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+-- Date        : Fri Sep 25 22:25:05 2026
+-- Host        : IRON-B running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gpll_sim_netlist.vhdl
+-- Design      : gpll
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a35tcpg236-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz is
+  signal clk_in1_gpll : STD_LOGIC;
+  signal clk_out1_gpll : STD_LOGIC;
+  signal clkfbout_buf_gpll : STD_LOGIC;
+  signal clkfbout_gpll : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_gpll,
+      O => clkfbout_buf_gpll
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_gpll
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_out1_gpll,
+      O => clk_out1
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 9,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 10.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 3,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 1,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 1,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_gpll,
+      CLKFBOUT => clkfbout_gpll,
+      CLKIN1 => clk_in1_gpll,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => clk_out1_gpll,
+      CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+      CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gpll_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      clk_out1 => clk_out1,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.v
new file mode 100755
index 0000000..84f4608
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+// Date        : Fri Sep 25 22:25:05 2026
+// Host        : IRON-B running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gpll_stub.v
+// Design      : gpll
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a35tcpg236-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* CORE_GENERATION_INFO = "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+  output clk_out1 /* synthesis syn_isclock = 1 */;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.vhdl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.vhdl
new file mode 100755
index 0000000..6c019f2
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip/2026.1/d/2/d2fa91287cc072e8/gpll_stub.vhdl
@@ -0,0 +1,34 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+-- Date        : Fri Sep 25 22:25:05 2026
+-- Host        : IRON-B running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gpll_stub.vhdl
+-- Design      : gpll
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a35tcpg236-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  attribute syn_black_box : boolean;
+  attribute black_box_pad_pin : string;
+  attribute syn_black_box of stub : architecture is true;
+  attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/synthesis.wdf b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/synthesis.wdf
index a93edb2..2e9d276 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/synthesis.wdf
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/synthesis.wdf
@@ -46,7 +46,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323873:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323934392e3332304d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313136312e3933384d42:00:00
-eof:2303255707
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a323673:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323936362e3035394d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313137352e3638304d42:00:00
+eof:38523470
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/webtalk_pa.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/webtalk_pa.xml
index f085c28..49ac383 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/webtalk_pa.xml
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt/webtalk_pa.xml
@@ -3,10 +3,10 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Fri Sep 25 21:30:17 2026">
+<application name="pa" timeStamp="Fri Sep 25 22:24:28 2026">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="08d678ffcad7427e99e7ce98a8e47219" type="ProjectID"/>
-<property name="ProjectIteration" value="2" type="ProjectIteration"/>
+<property name="ProjectIteration" value="3" type="ProjectIteration"/>
 </section>
 <section name="PlanAhead Usage" visible="true">
 <item name="Project Data">
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/doc/clk_wiz_v6_0_changelog.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/doc/clk_wiz_v6_0_changelog.txt
new file mode 100755
index 0000000..4ad063c
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/doc/clk_wiz_v6_0_changelog.txt
@@ -0,0 +1,363 @@
+2026.1:
+ * Version 6.0 (Rev. 19)
+ * General: Updated for 2026.1
+
+2025.2.1:
+ * Version 6.0 (Rev. 18)
+ * General: Updated IP Catalog taxonomy structure. This change has no impact to the IP.
+
+2025.2:
+ * Version 6.0 (Rev. 17)
+ * General: Updated for 2025.2
+
+2025.1.1:
+ * Version 6.0 (Rev. 16)
+ * No changes
+
+2025.1:
+ * Version 6.0 (Rev. 16)
+ * General: Updated IP Catalog taxonomy structure. This change has no impact to the IP.
+
+2024.2.2:
+ * Version 6.0 (Rev. 15)
+ * No changes
+
+2024.2.1:
+ * Version 6.0 (Rev. 15)
+ * No changes
+
+2024.2:
+ * Version 6.0 (Rev. 15)
+ * General: Updated for 2024.2
+
+2024.1.2:
+ * Version 6.0 (Rev. 14)
+ * No changes
+
+2024.1.1:
+ * Version 6.0 (Rev. 14)
+ * No changes
+
+2024.1:
+ * Version 6.0 (Rev. 14)
+ * General: IP packaging adjustments to address warnings from IP Packager integrity check
+
+2023.2.2:
+ * Version 6.0 (Rev. 13)
+ * No changes
+
+2023.2.1:
+ * Version 6.0 (Rev. 13)
+ * No changes
+
+2023.2:
+ * Version 6.0 (Rev. 13)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2023.1.2:
+ * Version 6.0 (Rev. 12)
+ * No changes
+
+2023.1.1:
+ * Version 6.0 (Rev. 12)
+ * No changes
+
+2023.1:
+ * Version 6.0 (Rev. 12)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.2.2:
+ * Version 6.0 (Rev. 11)
+ * No changes
+
+2022.2.1:
+ * Version 6.0 (Rev. 11)
+ * No changes
+
+2022.2:
+ * Version 6.0 (Rev. 11)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.1.2:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1.1:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1:
+ * Version 6.0 (Rev. 10)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.2.2:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2.1:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2:
+ * Version 6.0 (Rev. 9)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.1.1:
+ * Version 6.0 (Rev. 8)
+ * No changes
+
+2021.1:
+ * Version 6.0 (Rev. 8)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.3:
+ * Version 6.0 (Rev. 7)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.2.2:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2.1:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2:
+ * Version 6.0 (Rev. 6)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.1.1:
+ * Version 6.0 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 6.0 (Rev. 5)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.2.2:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2.1:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 6.0 (Rev. 4)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.1.3:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 6.0 (Rev. 3)
+ * Bug Fix: Internal GUI fixes
+ * Other: New family support added
+
+2018.3.1:
+ * Version 6.0 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 6.0 (Rev. 2)
+ * Bug Fix: Made input source independent for primary and secondary clock
+ * Other: New family support added
+
+2018.2:
+ * Version 6.0 (Rev. 1)
+ * Bug Fix: Removed vco freq check when Primitive is None
+ * Other: New family support added
+
+2018.1:
+ * Version 6.0
+ * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
+ * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
+ * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
+ * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
+ * Other: DRCs added for invalid input values in Override mode
+
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2026 Advanced Micro Devices, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of AMD and is protected under U.S. and international copyright
+and other intellectual property laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+AMD, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) AMD shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or AMD had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+AMD products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of AMD products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.dcp
new file mode 100644
index 0000000..cad1627
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.dcp
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.v
new file mode 100644
index 0000000..f02959f
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.v
@@ -0,0 +1,90 @@
+
+// file: gpll.v
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__300.00000______0.000______50.0______111.879____105.461
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+`default_nettype wire
+
+(* CORE_GENERATION_INFO = "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module gpll 
+ (
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  input         reset,
+  output        locked,
+ // Clock in ports
+  input         clk_in1
+ );
+
+  gpll_clk_wiz inst
+  (
+  // Clock out ports  
+  .clk_out1(clk_out1),
+  // Status and control signals               
+  .reset(reset), 
+  .locked(locked),
+ // Clock in ports
+  .clk_in1(clk_in1)
+  );
+
+endmodule
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.veo b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.veo
new file mode 100644
index 0000000..d952a9a
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.veo
@@ -0,0 +1,79 @@
+
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__300.00000______0.000______50.0______111.879____105.461
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  gpll instance_name
+   (
+    // Clock out ports
+    .clk_out1(clk_out1),     // output clk_out1
+    // Status and control signals
+    .reset(reset), // input reset
+    .locked(locked),       // output locked
+   // Clock in ports
+    .clk_in1(clk_in1)      // input clk_in1
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xdc b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xdc
new file mode 100644
index 0000000..3430052
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xdc
@@ -0,0 +1,57 @@
+
+# file: gpll.xdc
+# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# AMD, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) AMD shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or AMD had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# AMD products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of AMD products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc 
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.000 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xml
new file mode 100644
index 0000000..6c5f324
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll.xml
@@ -0,0 +1,5025 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>customized_ip</spirit:library>
+  <spirit:name>gpll</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi_lite</spirit:name>
+      <spirit:displayName>S_AXI_LITE</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>DATA_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PROTOCOL</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ID_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ADDR_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>AWUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ARUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BUSER_WIDTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>READ_WRITE_MODE</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_LOCK</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_PROT</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_CACHE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_QOS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_REGION</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_WSTRB</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_BRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>HAS_RRESP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>MAX_BURST_LENGTH</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_READ_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>NUM_WRITE_THREADS</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_lite" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aclk</spirit:name>
+      <spirit:displayName>s_axi_aclk</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi_lite</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_aclk" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ref_clk</spirit:name>
+      <spirit:displayName>ref_clk</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ref_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.ref_clk" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_resetn</spirit:name>
+      <spirit:displayName>S_AXI_RESETN</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.ASSOCIATED_RESET">aresetn</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_resetn" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>intr</spirit:name>
+      <spirit:displayName>Intr</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>INTERRUPT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>interrupt</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>SENSITIVITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.INTR.SENSITIVITY">EDGE_RISING</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PortWidth</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.intr" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK_IN1_D</spirit:name>
+      <spirit:displayName>CLK_IN1_D</spirit:displayName>
+      <spirit:description>Differential Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_in1_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_in1_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_IN1_D" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLK_IN2_D</spirit:name>
+      <spirit:displayName>CLK_IN2_D</spirit:displayName>
+      <spirit:description>Differential Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_in2_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_in2_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_IN2_D.BOARD.ASSOCIATED_PARAM">CLK_IN2_BOARD_INTERFACE</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:enablement>
+                <xilinx:presence>required</xilinx:presence>
+              </xilinx:enablement>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLK_IN2_D" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER&apos;))=1))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLKFB_IN_D</spirit:name>
+      <spirit:displayName>CLKFB_IN_D</spirit:displayName>
+      <spirit:description>Differential Feedback Clock input</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkfb_in_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkfb_in_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_IN_D" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>CLKFB_OUT_D</spirit:name>
+      <spirit:displayName>CLKFB_OUT_D</spirit:displayName>
+      <spirit:description>Differential Feeback Clock Output</spirit:description>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_N</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkfb_out_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_P</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clkfb_out_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>CAN_DEBUG</spirit:name>
+          <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.CLKFB_OUT_D" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>reset</spirit:name>
+      <spirit:displayName>reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_RESET&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_RESET_LOW&apos;))=0) and (not spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;)))">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>resetn</spirit:name>
+      <spirit:displayName>resetn</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>resetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.RESETN.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_RESET&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_RESET_LOW&apos;))=1) and (not spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;)))">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:busInterfaceInfo>
+      </spirit:vendorExtensions>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clock_CLK_IN1</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_IN1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_in1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.BOARD.ASSOCIATED_PARAM">CLK_IN1_BOARD_INTERFACE</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>clock_CLK_OUT1</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK_OUT1</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk_out1</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>FREQ_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>PHASE</spirit:name>
+          <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>CLK_DOMAIN</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_PORT</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_PORT"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>none</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>INSERT_VIP</spirit:name>
+          <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:value>
+          <spirit:vendorExtensions>
+            <xilinx:parameterInfo>
+              <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
+            </xilinx:parameterInfo>
+          </spirit:vendorExtensions>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:modelName>clk_wiz_v6_0_19</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:18 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:02208df5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesimulationwrapper</spirit:name>
+        <spirit:displayName>Simulation Wrapper</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
+        <spirit:modelName>gpll</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:18 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:02208df5</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:modelName>clk_wiz_v6_0_19</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:18 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesiswrapper</spirit:name>
+        <spirit:displayName>Synthesis Wrapper</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
+        <spirit:modelName>gpll</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:18 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_blockmodel</spirit:name>
+        <spirit:displayName>Block Model files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:block_model</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_elaborateports</spirit:name>
+        <spirit:displayName>Elaborate Ports</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:elaborate.ports</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:80bb0897</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_externalfiles</spirit:name>
+        <spirit:displayName>External Files</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:25:06 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_implementation</spirit:name>
+        <spirit:displayName>Implementation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:implementation</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_implementation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:19 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_synthesisconstraints</spirit:name>
+        <spirit:displayName>Synthesis Constraints</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
+        <spirit:displayName>Verilog Instantiation Template</spirit:displayName>
+        <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
+        <spirit:language>verilog</spirit:language>
+        <spirit:modelName>clk_wiz_v6_0_19</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:03 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_versioninformation</spirit:name>
+        <spirit:displayName>Version Information</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>GENtimestamp</spirit:name>
+            <spirit:value>Fri Sep 25 22:22:19 UTC 2026</spirit:value>
+          </spirit:parameter>
+          <spirit:parameter>
+            <spirit:name>outputProductCRC</spirit:name>
+            <spirit:value>9:e5ab88d9</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>s_axi_aclk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_aclk" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_aresetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_aresetn" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_awaddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH&apos;)) - 1)">10</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awaddr" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_awvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awvalid" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_awready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_awready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_wdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wdata" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_wstrb</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) div 8) - 1)">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wstrb" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_wvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wvalid" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_wready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_wready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_bresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bresp" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_bvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bvalid" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_bready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_bready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_araddr</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH&apos;)) - 1)">10</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_araddr" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arvalid" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_arready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_arready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rdata" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rresp" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rvalid" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.s_axi_rready" xilinx:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_in1_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in1_p" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_in1_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in1_n" xilinx:dependency="((spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_PRIM_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_in2_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in2_p" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER&apos;))=1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_in2_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_in2_n" xilinx:dependency="(((spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_clock_capable_pin&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_SECONDARY_SOURCE&apos;))=&quot;Differential_non_clock_pin&quot;)) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER&apos;))=1))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkfb_in_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_p" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkfb_in_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_in_n" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkfb_out_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_p" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clkfb_out_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clkfb_out_n" xilinx:dependency="((((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))!=&quot;FDBK_AUTO&quot;) or (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;))) or ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;)) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_FEEDBACK_SOURCE&apos;))=&quot;FDBK_AUTO_OFFCHIP&quot;) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING&apos;))=&quot;DIFF&quot;) and ((spirit:decode(id(&apos;MODELPARAM_VALUE.C_MMCM_COMPENSATION&apos;))!=&quot;INTERNAL&quot;))))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>reset</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.reset" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_RESET&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_RESET_LOW&apos;))=0) and (not spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;)))">true</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>resetn</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.resetn" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_USE_RESET&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_RESET_LOW&apos;))=1) and (not spirit:decode(id(&apos;MODELPARAM_VALUE.C_INTERFACE_SELECTION&apos;)))">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ref_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ref_clk" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_stop</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_stop" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_glitch</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_glitch" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>interrupt</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.interrupt" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_oor</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">3</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic_vector</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.clk_oor" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>user_clk0</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk0" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_Enable_PLL0&apos;))=0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>user_clk1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk1" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_Enable_PLL1&apos;))=0)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>user_clk2</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk2" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>user_clk3</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+        <spirit:vendorExtensions>
+          <xilinx:portInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.user_clk3" xilinx:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR&apos;))=1) and (spirit:decode(id(&apos;MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3&apos;))=1)">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:portInfo>
+        </spirit:vendorExtensions>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_in1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_out1</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>locked</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT2_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_USED" spirit:order="194">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USER_CLK_FREQ0</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ0" spirit:order="1194">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="string">
+        <spirit:name>C_AUTO_PRIMITIVE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUTO_PRIMITIVE" spirit:order="1195">MMCM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USER_CLK_FREQ1</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ1" spirit:order="1195">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USER_CLK_FREQ2</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ2" spirit:order="1196">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USER_CLK_FREQ3</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USER_CLK_FREQ3" spirit:order="1197">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_CLOCK_MONITOR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR" spirit:order="1200">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_USER_CLOCK0</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0" spirit:order="1201">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_USER_CLOCK1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1" spirit:order="1202">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_USER_CLOCK2</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2" spirit:order="1203">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_USER_CLOCK3</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3" spirit:order="1204">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_Enable_PLL0</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_Enable_PLL0" spirit:order="1205">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_Enable_PLL1</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_Enable_PLL1" spirit:order="1206">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_REF_CLK_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_REF_CLK_FREQ" spirit:order="1209">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PRECISION</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRECISION" spirit:order="1209">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT3_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_USED" spirit:order="195">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT4_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_USED" spirit:order="196">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT5_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_USED" spirit:order="197">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT6_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_USED" spirit:order="198">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT7_USED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_USED" spirit:order="199">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLKOUT1_BAR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR" spirit:order="200">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLKOUT2_BAR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR" spirit:order="201">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLKOUT3_BAR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR" spirit:order="202">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLKOUT4_BAR</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR" spirit:order="203">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>c_component_name</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_component_name">gpll</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLATFORM</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLATFORM" spirit:order="204">UNKNOWN</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_FREQ_SYNTH</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREQ_SYNTH" spirit:order="205">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_PHASE_ALIGNMENT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT" spirit:order="206">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIM_IN_JITTER</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_JITTER" spirit:order="207">0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SECONDARY_IN_JITTER</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER" spirit:order="208">0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_JITTER_SEL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_JITTER_SEL" spirit:order="209">No_Jitter</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_MIN_POWER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_POWER" spirit:order="210">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_MIN_O_JITTER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_O_JITTER" spirit:order="211">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_MAX_I_JITTER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MAX_I_JITTER" spirit:order="212">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DYN_PHASE_SHIFT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT" spirit:order="213">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="214">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_INCLK_SWITCHOVER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER" spirit:order="214">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_DYN_RECONFIG</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_RECONFIG" spirit:order="215">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SPREAD_SPECTRUM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM" spirit:order="216">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_FAST_SIMULATION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FAST_SIMULATION" spirit:order="217">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIMTYPE_SEL</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMTYPE_SEL" spirit:order="218">AUTO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLK_VALID</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLK_VALID" spirit:order="219">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIM_IN_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_FREQ" spirit:order="220">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIM_IN_TIMEPERIOD</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD" spirit:order="220.001">10.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_IN_FREQ_UNITS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IN_FREQ_UNITS" spirit:order="221">Units_MHz</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SECONDARY_IN_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ" spirit:order="222">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SECONDARY_IN_TIMEPERIOD</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD" spirit:order="222.001">10.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_FEEDBACK_SOURCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FEEDBACK_SOURCE" spirit:order="223">FDBK_AUTO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIM_SOURCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PHASESHIFT_MODE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PHASESHIFT_MODE" spirit:order="2240">WAVEFORM</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SECONDARY_SOURCE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_SOURCE" spirit:order="225">Single_ended_clock_capable_pin</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_IN_SIGNALING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING" spirit:order="226">SINGLE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_RESET</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_RESET_LOW</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_LOCKED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_POWER_DOWN</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_STATUS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_FREEZE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+        <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">clk_out1__300.00000______0.000______50.0______111.879____105.461</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">no_CLK_OUT2_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">no_CLK_OUT3_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">no_CLK_OUT4_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">300.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">300.00000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_NOTES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">9.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">3.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_NOTES</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_COMPENSATION</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_REF_JITTER</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_OVERRIDE_PLL</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIMARY_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SECONDARY_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_RESET_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_LOCKED_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DADDR_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DCLK_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DRDY_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DWE_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIN_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DOUT_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DEN_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PSCLK_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PSEN_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PSINCDEC_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PSDONE_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_VALID_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_STATUS_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PRIMITIVE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">PLL</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SS_MODE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_SS_MOD_TIME</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_HAS_CDDC</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CDDCDONE_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CDDCREQ_PORT</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="INTEGER">
+        <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>C S Axi Data Width</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_POWER_REG</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_REG" spirit:order="409">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT0_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT0_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_2" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_1" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFBOUT_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_1" spirit:order="410">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKFBOUT_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVCLK</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVCLK" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_LOCK_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_1" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_LOCK_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_LOCK_3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_3" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_FILTER_1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_1" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_FILTER_2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_2" spirit:order="411">0000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE1_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE1_AUTO" spirit:order="411">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE2_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE3_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE3_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE4_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE4_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE5_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE5_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE6_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE6_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_DIVIDE7_AUTO</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE7_AUTO" spirit:order="411">0.3333333333333333</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLLBUFGCEDIV</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLLBUFGCEDIV1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV1" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLLBUFGCEDIV2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV2" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLLBUFGCEDIV3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV3" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_PLLBUFGCEDIV4</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV4" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV1</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV2</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV3</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV4</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV5</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV6</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_MMCMBUFGCEDIV7</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT7_MATCHED_ROUTING</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT0_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ" spirit:order="711">300.00000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ" spirit:order="713">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT3_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ" spirit:order="714">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT4_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ" spirit:order="715">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT5_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ" spirit:order="716">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="STRING">
+        <spirit:name>C_CLKOUT6_ACTUAL_FREQ</spirit:name>
+        <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ" spirit:order="717">100.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_M_MAX</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MAX" spirit:order="403">64.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_M_MIN</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MIN" spirit:order="403">2.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_D_MAX</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MAX" spirit:order="403">42.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_D_MIN</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MIN" spirit:order="403">1.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_O_MAX</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MAX" spirit:order="403">128.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_O_MIN</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MIN" spirit:order="403">1.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_VCO_MIN</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MIN" spirit:order="403">800.000</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="REAL">
+        <spirit:name>C_VCO_MAX</spirit:name>
+        <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MAX" spirit:order="403">1600.000</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_1d3de01d</spirit:name>
+      <spirit:enumeration>WAVEFORM</spirit:enumeration>
+      <spirit:enumeration>LATENCY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_876bfc32</spirit:name>
+      <spirit:enumeration>UI</spirit:enumeration>
+      <spirit:enumeration>PS</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_a9bdfce0</spirit:name>
+      <spirit:enumeration>LOW</spirit:enumeration>
+      <spirit:enumeration>HIGH</spirit:enumeration>
+      <spirit:enumeration>OPTIMIZED</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_ac75ef1e</spirit:name>
+      <spirit:enumeration>Custom</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_b9d38208</spirit:name>
+      <spirit:enumeration>CLKFBOUT</spirit:enumeration>
+      <spirit:enumeration>CLKOUT0</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_e099fe6c</spirit:name>
+      <spirit:enumeration>MMCM</spirit:enumeration>
+      <spirit:enumeration>PLL</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_035ca1c3</spirit:name>
+      <spirit:enumeration spirit:text="SYSTEM SYNCHRONOUS">SYSTEM_SYNCHRONOUS</spirit:enumeration>
+      <spirit:enumeration spirit:text="SOURCE SYNCHRONOUS">SOURCE_SYNCHRONOUS</spirit:enumeration>
+      <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+      <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_0920eb1b</spirit:name>
+      <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+      <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_11d71346</spirit:name>
+      <spirit:enumeration spirit:text="Single ended clock capable pin">Single_ended_clock_capable_pin</spirit:enumeration>
+      <spirit:enumeration spirit:text="Differential clock capable pin">Differential_clock_capable_pin</spirit:enumeration>
+      <spirit:enumeration spirit:text="Global buffer">Global_buffer</spirit:enumeration>
+      <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_15c806d5</spirit:name>
+      <spirit:enumeration spirit:text="Automatic Control On-Chip">FDBK_AUTO</spirit:enumeration>
+      <spirit:enumeration spirit:text="Automatic Control Off-Chip">FDBK_AUTO_OFFCHIP</spirit:enumeration>
+      <spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
+      <spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_340369e0</spirit:name>
+      <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+      <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
+      <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_3c2d3ec7</spirit:name>
+      <spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
+      <spirit:enumeration spirit:text="Differential">DIFF</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_502d9f23</spirit:name>
+      <spirit:enumeration spirit:text="ZHOLD">ZHOLD</spirit:enumeration>
+      <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+      <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+      <spirit:enumeration spirit:text="BUF IN">BUF_IN</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_66e4c81f</spirit:name>
+      <spirit:enumeration spirit:text="BUFG">BUFG</spirit:enumeration>
+      <spirit:enumeration spirit:text="BUFH">BUFH</spirit:enumeration>
+      <spirit:enumeration spirit:text="BUFGCE">BUFGCE</spirit:enumeration>
+      <spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
+      <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_77d3d587</spirit:name>
+      <spirit:enumeration spirit:text="MMCM">MMCM</spirit:enumeration>
+      <spirit:enumeration spirit:text="PLL">PLL</spirit:enumeration>
+      <spirit:enumeration spirit:text="BUFGCE DIV">BUFGCE_DIV</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8b28f1f7</spirit:name>
+      <spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
+      <spirit:enumeration spirit:text="DRP">Enable_DRP</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_8eea9b32</spirit:name>
+      <spirit:enumeration spirit:text="Units MHz">Units_MHz</spirit:enumeration>
+      <spirit:enumeration spirit:text="Units ns">Units_ns</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a4fbc00c</spirit:name>
+      <spirit:enumeration spirit:text="Active High">ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration spirit:text="Active Low">ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a8642b4c</spirit:name>
+      <spirit:enumeration spirit:text="Balanced">No_Jitter</spirit:enumeration>
+      <spirit:enumeration spirit:text="Minimize Output Jitter">Min_O_Jitter</spirit:enumeration>
+      <spirit:enumeration spirit:text="Maximize Input Jitter filtering">Max_I_Jitter</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_c5ef7212</spirit:name>
+      <spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
+      <spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_e1c87518</spirit:name>
+      <spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
+      <spirit:enumeration spirit:text="Secondary Clock">REL_SECONDARY</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f4e10086</spirit:name>
+      <spirit:enumeration spirit:text="CENTER HIGH">CENTER_HIGH</spirit:enumeration>
+      <spirit:enumeration spirit:text="CENTER LOW">CENTER_LOW</spirit:enumeration>
+      <spirit:enumeration spirit:text="DOWN HIGH">DOWN_HIGH</spirit:enumeration>
+      <spirit:enumeration spirit:text="DOWN LOW">DOWN_LOW</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_f669c2f5</spirit:name>
+      <spirit:enumeration spirit:text="Frequency">frequency</spirit:enumeration>
+      <spirit:enumeration spirit:text="Time">Time</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_clk_wiz.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:define>
+          <spirit:name>processing_order</spirit:name>
+          <spirit:value>early</spirit:value>
+        </spirit:define>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_ooc.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:isIncludeFile>true</spirit:isIncludeFile>
+        <spirit:logicalName>clk_wiz_v6_0_19</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_clk_wiz.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll.dcp</spirit:name>
+        <spirit:userFileType>dcp</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_stub.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_stub.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_sim_netlist.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>gpll_sim_netlist.vhdl</spirit:name>
+        <spirit:fileType>vhdlSource</spirit:fileType>
+        <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+        <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll_board.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+        <spirit:userFileType>USED_IN_board</spirit:userFileType>
+        <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+        <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gpll.veo</spirit:name>
+        <spirit:userFileType>verilogTemplate</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>doc/clk_wiz_v6_0_changelog.txt</spirit:name>
+        <spirit:userFileType>text</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user&apos;s clocking requirements.</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">gpll</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USER_CLK_FREQ0</spirit:name>
+      <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ0" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USER_CLK_FREQ1</spirit:name>
+      <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ1" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USER_CLK_FREQ2</spirit:name>
+      <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ2" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USER_CLK_FREQ3</spirit:name>
+      <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ3" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_CLOCK_MONITOR</spirit:name>
+      <spirit:displayName>Enable Clock Monitoring</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLOCK_MONITOR" spirit:order="10.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+      <spirit:displayName>Optimize Clocking Structure</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="10.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_USER_CLOCK0</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK0" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_USER_CLOCK1</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK1" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_USER_CLOCK2</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK2" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_USER_CLOCK3</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK3" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_PLL0</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL0" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Enable_PLL1</spirit:name>
+      <spirit:displayName>User Clock</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL1" spirit:order="1090">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>REF_CLK_FREQ</spirit:name>
+      <spirit:displayName>Reference Frequency(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:order="15300" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRECISION</spirit:name>
+      <spirit:displayName>Tolerance(MHz)</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRECISION" spirit:order="15400" spirit:minimum="1" spirit:maximum="100">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIMITIVE</spirit:name>
+      <spirit:displayName>Primitive</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">PLL</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIMTYPE_SEL</spirit:name>
+      <spirit:displayName>Primtype Sel</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+      <spirit:displayName>Clock Mgr Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FREQ_SYNTH</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_MIN_POWER</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_DYN_RECONFIG</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>JITTER_SEL</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_IN_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN_FREQ_UNITS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PHASESHIFT_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHASESHIFT_MODE" spirit:choiceRef="choice_list_1d3de01d" spirit:order="116" spirit:configGroups="0 NoDisplay">WAVEFORM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IN_JITTER_UNITS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RELATIVE_INCLK</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_SOURCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>JITTER_OPTIONS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_IN_JITTER</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_USED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>NUM_OUT_CLKS</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIMARY_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT1_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT2_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT3_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT4_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT5_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT6_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_OUT7_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DADDR_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DCLK_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DRDY_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DWE_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIN_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DOUT_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DEN_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PSCLK_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PSEN_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PSINCDEC_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PSDONE_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">300.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_MAX_I_JITTER</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_MIN_O_JITTER</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING" spirit:order="984" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING" spirit:order="985" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING" spirit:order="986" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING" spirit:order="987" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING" spirit:order="988" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING" spirit:order="989" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_MATCHED_ROUTING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING" spirit:order="990" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PRIM_SOURCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_DRIVES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FEEDBACK_SOURCE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_IN_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_OUT_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLATFORM</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SUMMARY_STRINGS</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_LOCKED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CALC_DONE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_RESET</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">true</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_POWER_DOWN</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_STATUS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_FREEZE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_CLK_VALID</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_INCLK_STOPPED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">reset</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>LOCKED_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>POWER_DOWN_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_VALID_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>STATUS_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SS_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SS_MOD_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SS_MOD_TIME</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OVERRIDE_MMCM</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_NOTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_BANDWIDTH</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">9</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_COMPENSATION</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_REF_JITTER1</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_REF_JITTER2</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">3</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>OVERRIDE_PLL</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_NOTES</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_BANDWIDTH</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_COMPENSATION</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_REF_JITTER</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_TYPE</spirit:name>
+      <spirit:displayName>Reset Type</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_HIGH</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USE_BOARD_FLOW</spirit:name>
+      <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.8">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.9">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AUTO_PRIMITIVE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AUTO_PRIMITIVE" spirit:choiceRef="choice_pairs_77d3d587" spirit:order="13212">MMCM</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_CDDC</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CDDCDONE_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CDDCREQ_PORT</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_JITTER</spirit:name>
+      <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">111.879</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout1 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">105.461</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_JITTER</spirit:name>
+      <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout2 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_JITTER</spirit:name>
+      <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout3 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_JITTER</spirit:name>
+      <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout4 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_JITTER</spirit:name>
+      <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout5 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_JITTER</spirit:name>
+      <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout6 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_JITTER</spirit:name>
+      <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+      <spirit:displayName>Clkout7 Phase</spirit:displayName>
+      <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INPUT_MODE</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="7.8">frequency</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>INTERFACE_SELECTION</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_DRP</spirit:name>
+      <spirit:displayName>Write DRP registers</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_DRP" spirit:order="11.12">false</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+      <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+      <xilinx:xpmLibraries>
+        <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+      </xilinx:xpmLibraries>
+      <xilinx:coreRevision>19</xilinx:coreRevision>
+      <xilinx:configElementInfos>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
+        <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
+      </xilinx:configElementInfos>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2026.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="52494094"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7e567b44"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c11c59cd"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="63dcade9"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_board.xdc b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_board.xdc
new file mode 100644
index 0000000..3422a8e
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v
new file mode 100644
index 0000000..55853ad
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v
@@ -0,0 +1,177 @@
+
+// file: gpll.v
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__300.00000______0.000______50.0______111.879____105.461
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+`default_nettype wire
+
+module gpll_clk_wiz 
+
+ (// Clock in ports
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  input         reset,
+  output        locked,
+  input         clk_in1
+ );
+  // Input buffering
+  //------------------------------------
+wire clk_in1_gpll;
+wire clk_in1_gpll_buf;
+wire clk_in2_gpll;
+  IBUF clkin1_ibufg
+   (.O (clk_in1_gpll),
+    .I (clk_in1));
+
+
+
+
+  // Clocking PRIMITIVE
+  //------------------------------------
+
+  // Instantiation of the MMCM PRIMITIVE
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+
+  wire        clk_out1_gpll;
+
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        psdone_unused;
+  wire        locked_int;
+  wire        clkfbout_gpll;
+  wire        clkfbout_buf_gpll;
+  wire        clkfboutb_unused;
+   wire clkout1_unused;
+   wire clkout2_unused;
+   wire clkout3_unused;
+   wire clkout4_unused;
+  wire        clkout5_unused;
+  wire        clkout6_unused;
+  wire        clkfbstopped_unused;
+  wire        clkinstopped_unused;
+  wire        reset_high;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("ZHOLD"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (9),
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (3),
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (10.000))
+  plle2_adv_inst
+    // Output clocks
+   (
+    .CLKFBOUT            (clkfbout_gpll),
+    .CLKOUT0             (clk_out1_gpll),
+    .CLKOUT1             (clkout1_unused),
+    .CLKOUT2             (clkout2_unused),
+    .CLKOUT3             (clkout3_unused),
+    .CLKOUT4             (clkout4_unused),
+    .CLKOUT5             (clkout5_unused),
+     // Input clock control
+    .CLKFBIN             (clkfbout_buf_gpll),
+    .CLKIN1              (clk_in1_gpll),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
+    .CLKINSEL            (1'b1),
+    // Ports for dynamic reconfiguration
+    .DADDR               (7'h0),
+    .DCLK                (1'b0),
+    .DEN                 (1'b0),
+    .DI                  (16'h0),
+    .DO                  (do_unused),
+    .DRDY                (drdy_unused),
+    .DWE                 (1'b0),
+    // Other control and status signals
+    .LOCKED              (locked_int),
+    .PWRDWN              (1'b0),
+    .RST                 (reset_high));
+  assign reset_high = reset; 
+
+  assign locked = locked_int;
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+  //-----------------------------------
+
+  BUFG clkf_buf
+   (.O (clkfbout_buf_gpll),
+    .I (clkfbout_gpll));
+
+
+
+
+
+
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_gpll));
+
+
+
+
+endmodule
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_ooc.xdc b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_ooc.xdc
new file mode 100644
index 0000000..6a0d66f
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_ooc.xdc
@@ -0,0 +1,55 @@
+
+# file: gpll_ooc.xdc
+# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of AMD and is protected under U.S. and international copyright
+# and other intellectual property laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# AMD, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) AMD shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or AMD had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# AMD products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of AMD products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints                                 #
+############################################################
+#create_clock -period 10.000 [get_ports clk_in1]
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.v
new file mode 100644
index 0000000..892cde4
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.v
@@ -0,0 +1,220 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+// Date        : Fri Sep 25 22:25:06 2026
+// Host        : IRON-B running 64-bit unknown
+// Command     : write_verilog -force -mode funcsim
+//               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.v
+// Design      : gpll
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a35tcpg236-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module gpll
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  (* IBUF_LOW_PWR *) wire clk_in1;
+  wire clk_out1;
+  wire locked;
+  wire reset;
+
+  gpll_clk_wiz inst
+       (.clk_in1(clk_in1),
+        .clk_out1(clk_out1),
+        .locked(locked),
+        .reset(reset));
+endmodule
+
+module gpll_clk_wiz
+   (clk_out1,
+    reset,
+    locked,
+    clk_in1);
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+
+  wire clk_in1;
+  wire clk_in1_gpll;
+  wire clk_out1;
+  wire clk_out1_gpll;
+  wire clkfbout_buf_gpll;
+  wire clkfbout_gpll;
+  wire locked;
+  wire reset;
+  wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
+  wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
+  wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
+  wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
+
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkf_buf
+       (.I(clkfbout_gpll),
+        .O(clkfbout_buf_gpll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  (* CAPACITANCE = "DONT_CARE" *) 
+  (* IBUF_DELAY_VALUE = "0" *) 
+  (* IFD_DELAY_VALUE = "AUTO" *) 
+  IBUF #(
+    .IOSTANDARD("DEFAULT")) 
+    clkin1_ibufg
+       (.I(clk_in1),
+        .O(clk_in1_gpll));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  BUFG clkout1_buf
+       (.I(clk_out1_gpll),
+        .O(clk_out1));
+  (* BOX_TYPE = "PRIMITIVE" *) 
+  PLLE2_ADV #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKFBOUT_MULT(9),
+    .CLKFBOUT_PHASE(0.000000),
+    .CLKIN1_PERIOD(10.000000),
+    .CLKIN2_PERIOD(0.000000),
+    .CLKOUT0_DIVIDE(3),
+    .CLKOUT0_DUTY_CYCLE(0.500000),
+    .CLKOUT0_PHASE(0.000000),
+    .CLKOUT1_DIVIDE(1),
+    .CLKOUT1_DUTY_CYCLE(0.500000),
+    .CLKOUT1_PHASE(0.000000),
+    .CLKOUT2_DIVIDE(1),
+    .CLKOUT2_DUTY_CYCLE(0.500000),
+    .CLKOUT2_PHASE(0.000000),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.500000),
+    .CLKOUT3_PHASE(0.000000),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.500000),
+    .CLKOUT4_PHASE(0.000000),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.500000),
+    .CLKOUT5_PHASE(0.000000),
+    .COMPENSATION("ZHOLD"),
+    .DIVCLK_DIVIDE(1),
+    .IS_CLKINSEL_INVERTED(1'b0),
+    .IS_PWRDWN_INVERTED(1'b0),
+    .IS_RST_INVERTED(1'b0),
+    .REF_JITTER1(0.010000),
+    .REF_JITTER2(0.010000),
+    .STARTUP_WAIT("FALSE")) 
+    plle2_adv_inst
+       (.CLKFBIN(clkfbout_buf_gpll),
+        .CLKFBOUT(clkfbout_gpll),
+        .CLKIN1(clk_in1_gpll),
+        .CLKIN2(1'b0),
+        .CLKINSEL(1'b1),
+        .CLKOUT0(clk_out1_gpll),
+        .CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
+        .CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
+        .CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
+        .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
+        .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
+        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DCLK(1'b0),
+        .DEN(1'b0),
+        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
+        .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
+        .DWE(1'b0),
+        .LOCKED(locked),
+        .PWRDWN(1'b0),
+        .RST(reset));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.vhdl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.vhdl
new file mode 100644
index 0000000..05fe139
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.vhdl
@@ -0,0 +1,151 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+-- Date        : Fri Sep 25 22:25:06 2026
+-- Host        : IRON-B running 64-bit unknown
+-- Command     : write_vhdl -force -mode funcsim
+--               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_sim_netlist.vhdl
+-- Design      : gpll
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a35tcpg236-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity gpll_clk_wiz is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+end gpll_clk_wiz;
+
+architecture STRUCTURE of gpll_clk_wiz is
+  signal clk_in1_gpll : STD_LOGIC;
+  signal clk_out1_gpll : STD_LOGIC;
+  signal clkfbout_buf_gpll : STD_LOGIC;
+  signal clkfbout_gpll : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+  signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+  attribute BOX_TYPE : string;
+  attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+  attribute CAPACITANCE : string;
+  attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+  attribute IBUF_DELAY_VALUE : string;
+  attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+  attribute IFD_DELAY_VALUE : string;
+  attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+  attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+  attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clkfbout_gpll,
+      O => clkfbout_buf_gpll
+    );
+clkin1_ibufg: unisim.vcomponents.IBUF
+    generic map(
+      IOSTANDARD => "DEFAULT"
+    )
+        port map (
+      I => clk_in1,
+      O => clk_in1_gpll
+    );
+clkout1_buf: unisim.vcomponents.BUFG
+     port map (
+      I => clk_out1_gpll,
+      O => clk_out1
+    );
+plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
+    generic map(
+      BANDWIDTH => "OPTIMIZED",
+      CLKFBOUT_MULT => 9,
+      CLKFBOUT_PHASE => 0.000000,
+      CLKIN1_PERIOD => 10.000000,
+      CLKIN2_PERIOD => 0.000000,
+      CLKOUT0_DIVIDE => 3,
+      CLKOUT0_DUTY_CYCLE => 0.500000,
+      CLKOUT0_PHASE => 0.000000,
+      CLKOUT1_DIVIDE => 1,
+      CLKOUT1_DUTY_CYCLE => 0.500000,
+      CLKOUT1_PHASE => 0.000000,
+      CLKOUT2_DIVIDE => 1,
+      CLKOUT2_DUTY_CYCLE => 0.500000,
+      CLKOUT2_PHASE => 0.000000,
+      CLKOUT3_DIVIDE => 1,
+      CLKOUT3_DUTY_CYCLE => 0.500000,
+      CLKOUT3_PHASE => 0.000000,
+      CLKOUT4_DIVIDE => 1,
+      CLKOUT4_DUTY_CYCLE => 0.500000,
+      CLKOUT4_PHASE => 0.000000,
+      CLKOUT5_DIVIDE => 1,
+      CLKOUT5_DUTY_CYCLE => 0.500000,
+      CLKOUT5_PHASE => 0.000000,
+      COMPENSATION => "ZHOLD",
+      DIVCLK_DIVIDE => 1,
+      IS_CLKINSEL_INVERTED => '0',
+      IS_PWRDWN_INVERTED => '0',
+      IS_RST_INVERTED => '0',
+      REF_JITTER1 => 0.010000,
+      REF_JITTER2 => 0.010000,
+      STARTUP_WAIT => "FALSE"
+    )
+        port map (
+      CLKFBIN => clkfbout_buf_gpll,
+      CLKFBOUT => clkfbout_gpll,
+      CLKIN1 => clk_in1_gpll,
+      CLKIN2 => '0',
+      CLKINSEL => '1',
+      CLKOUT0 => clk_out1_gpll,
+      CLKOUT1 => NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED,
+      CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
+      CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
+      CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
+      CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
+      DADDR(6 downto 0) => B"0000000",
+      DCLK => '0',
+      DEN => '0',
+      DI(15 downto 0) => B"0000000000000000",
+      DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
+      DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
+      DWE => '0',
+      LOCKED => locked,
+      PWRDWN => '0',
+      RST => reset
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity gpll is
+  port (
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of gpll : entity is true;
+end gpll;
+
+architecture STRUCTURE of gpll is
+begin
+inst: entity work.gpll_clk_wiz
+     port map (
+      clk_in1 => clk_in1,
+      clk_out1 => clk_out1,
+      locked => locked,
+      reset => reset
+    );
+end STRUCTURE;
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.v
new file mode 100644
index 0000000..b490c31
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+// Date        : Fri Sep 25 22:25:06 2026
+// Host        : IRON-B running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub
+//               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.v
+// Design      : gpll
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a35tcpg236-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* CORE_GENERATION_INFO = "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 
+module gpll(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+  output clk_out1 /* synthesis syn_isclock = 1 */;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.vhdl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.vhdl
new file mode 100644
index 0000000..d574eb2
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.vhdl
@@ -0,0 +1,34 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+-- Date        : Fri Sep 25 22:25:06 2026
+-- Host        : IRON-B running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.vhdl
+-- Design      : gpll
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a35tcpg236-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gpll is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of gpll : entity is "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
+end gpll;
+
+architecture stub of gpll is
+  attribute syn_black_box : boolean;
+  attribute black_box_pad_pin : string;
+  attribute syn_black_box of stub : architecture is true;
+  attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000..6c4981a
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1011_00,
+         10'b0010_1101_00,
+         10'b0010_0011_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0100_1111_00,
+         10'b0101_1011_00,
+         10'b0111_0111_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_1001_00,
+         10'b1101_0001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0111_0001_00,
+         10'b0111_0001_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0110_0001_00,
+         10'b0110_0001_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0100_1010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000..b662a3e
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,542 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+`ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+`ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+`endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+`ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+`ifdef DEBUG
+      $display("temp: %h", temp);
+`endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1101_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0011_0111_00,
+         10'b0011_0111_00,
+         10'b0101_1111_00,
+         10'b0111_1111_00,
+         10'b0111_1011_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_1101_00,
+         10'b1111_0111_00,
+         10'b1111_1011_00,
+         10'b1111_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+`endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+`ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000..154c81f
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_0011_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_1001_11,
+         10'b0010_1001_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1011_11,
+         10'b0011_1111_11,
+         10'b0100_1111_11,
+         10'b0100_1111_11,
+         10'b0101_1111_11,
+         10'b0110_1111_11,
+         10'b0111_1111_11,
+         10'b0111_1111_11,
+         10'b1100_1111_11,
+         10'b1101_1111_11,
+         10'b1110_1111_11,
+         10'b1111_1111_11,
+         10'b1111_1111_11,
+         10'b1110_0111_11,
+         10'b1110_1011_11,
+         10'b1111_0111_11,
+         10'b1111_1011_11,
+         10'b1111_1011_11,
+         10'b1110_1101_11,
+         10'b1111_1101_11,
+         10'b1111_1101_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000..ff369d1
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,555 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa
+//    Date:             6/15/2015
+//    Design Name:      PLLE3 DRP
+//    Module Name:      plle3_drp_func.h
+//    Version:          1.10
+//    Target Devices:   UltraScale Architecture
+//    Tool versions:    2015.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                         PM_Rise bits have been removed for PLLE3
+// 
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [759:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1  
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001 //19
+         
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 19
+   );
+   
+   reg [639:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0010_1111_01, //1
+         10'b0010_0011_11, //2
+         10'b0011_0011_11, //3
+         10'b0010_0001_11, //4
+         10'b0010_0110_11, //5
+         10'b0010_1010_11, //6
+         10'b0010_1010_11, //7
+         10'b0011_0110_11, //8
+         10'b0010_1100_11, //9
+         10'b0010_1100_11, //10
+         10'b0010_1100_11, //11
+         10'b0010_0010_11, //12
+         10'b0011_1100_11, //13
+         10'b0011_1100_11, //14
+         10'b0011_1100_11, //15
+         10'b0011_1100_11, //16
+         10'b0011_0010_11, //17
+         10'b0011_0010_11, //18
+         10'b0011_0010_11 //19
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+//			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000..fd26211
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,886 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa. Updated by Ralf Krueger
+//    Date:             7/30/2014
+//    Design Name:      MMCME4 DRP
+//    Module Name:      mmcme4_drp_func.h
+//    Version:          1.31
+//    Target Devices:   UltraScale Plus Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for UltraScal+ MMCM.
+//                      
+//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
+//				4/13 - Fractional divide function in mmcm_frac_count_calc function
+//              2/28/17 - Updated for Ultrascale Plus
+// 
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers.  These should not be modified, they are for development only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+// greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      // of 1 would modify the fractional so that instead of being a .16
+      // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//       is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      // assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [7:0] divide // Max M divide is 128 in UltrascalePlus
+   );
+   
+   reg [5119:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=1 (not allowed)
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=2
+         40'b01000_01000_1111101000_1111101001_0000000001,      // M=3
+         40'b01011_01011_1111101000_1111101001_0000000001,      // M=4
+         40'b01110_01110_1111101000_1111101001_0000000001,      // M=5
+         40'b10001_10001_1111101000_1111101001_0000000001,      // M=6
+         40'b10011_10011_1111101000_1111101001_0000000001,      // M=7
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,      // M=127
+         40'b11111_11111_0011111010_1111101001_0000000001       // M=128
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [7:0] divide, //  input [7:0] divide // Max M divide is 128 in UltraScalePlus
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [1279:0] lookup_low;
+   reg [1279:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+       	10'b0011_1111_11,    // M=1 - not legal
+       	10'b0011_1111_11,    // M=2
+       	10'b0011_1101_11,    // M=3
+       	10'b0011_0101_11,    // M=4
+       	10'b0011_1001_11,    // M=5
+       	10'b0011_1110_11,    // M=6
+       	10'b0011_1110_11,    // M=7
+       	10'b0011_0001_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0100_0110_11,
+       	10'b0011_1100_11,
+       	10'b1110_0110_11,
+       	10'b1111_0110_11,
+       	10'b1110_1010_11,
+       	10'b1110_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11, // M=127
+       	10'b1101_1000_11  // M=128
+};										
+      
+      lookup_high = {
+         // CP_RES_LFHF
+       10'b0111_1111_11,    // M=1 - not legal
+       10'b0111_1111_11,    // M=2
+       10'b1110_1111_11,    // M=3
+       10'b1111_1111_11,    // M=4
+       10'b1111_1011_11,    // M=5
+       10'b1111_1101_11,    // M=6
+       10'b1111_0011_11,    // M=7
+       10'b1110_0101_11,
+       10'b1111_1001_11,
+       10'b1111_1001_11,
+       10'b1110_1110_11,
+       10'b1111_1110_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1110_0110_11,
+       10'b1110_0110_11,
+       10'b1111_0110_11,
+       10'b1110_1010_11,
+       10'b1110_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11     // M=128
+};
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1);   //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);    //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000..0899943
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,561 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ 
+//    Date:             6/15/2015
+//    Design Name:      PLLE4 DRP
+//    Module Name:      plle4_drp_func.h
+//    Version:          2.0
+//    Target Devices:   UltraScale+ Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                           M_Rise bits have been removed for PLLE3
+//	Revision Notes:	2/28/17 - pll_filter_lookup and CPRES updated for 
+//                           Ultrascale+ and for max M of 21
+// 
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+         $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [839:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001, //19
+         40'b11111_11111_0111110100_1111101001_0000000001, //20
+         40'b11111_11111_0111011011_1111101001_0000000001  //21
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [209:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0011_0111_11, //1  not legal in Ultrascale+
+         10'b0011_0111_11, //2
+         10'b0011_0011_11, //3
+         10'b0011_1001_11, //4
+         10'b0011_0001_11, //5
+         10'b0100_1110_11, //6
+         10'b0011_0110_11, //7
+         10'b0011_1010_11, //8
+         10'b0111_1001_11, //9
+         10'b0111_1001_11, //10
+         10'b0101_0110_11, //11
+         10'b1100_0101_11, //12
+         10'b0101_1010_11, //13
+         10'b0110_0110_11, //14
+         10'b0110_1010_11, //15
+         10'b0111_0110_11, //16
+         10'b1111_0101_11, //17
+         10'b1100_0110_11, //18
+         10'b1110_0001_11, //19
+         10'b1101_0110_11, //20
+         10'b1111_0001_11  //21
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" 
+// will need to divide the doubled clock VCO clock frequency by 
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will 
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/README.txt
new file mode 100644
index 0000000..023052c
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll.veo b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll.veo
new file mode 100755
index 0000000..d952a9a
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll.veo
@@ -0,0 +1,79 @@
+
+// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__300.00000______0.000______50.0______111.879____105.461
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  gpll instance_name
+   (
+    // Clock out ports
+    .clk_out1(clk_out1),     // output clk_out1
+    // Status and control signals
+    .reset(reset), // input reset
+    .locked(locked),       // output locked
+   // Clock in ports
+    .clk_in1(clk_in1)      // input clk_in1
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.v
new file mode 100644
index 0000000..b490c31
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.v
@@ -0,0 +1,25 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+// Date        : Fri Sep 25 22:25:06 2026
+// Host        : IRON-B running 64-bit unknown
+// Command     : write_verilog -force -mode synth_stub
+//               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.v
+// Design      : gpll
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7a35tcpg236-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* CORE_GENERATION_INFO = "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 
+module gpll(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
+/* synthesis syn_force_seq_prim="clk_out1" */;
+  output clk_out1 /* synthesis syn_isclock = 1 */;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.vhdl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.vhdl
new file mode 100644
index 0000000..d574eb2
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ip/gpll/gpll_stub.vhdl
@@ -0,0 +1,34 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
+-- Date        : Fri Sep 25 22:25:06 2026
+-- Host        : IRON-B running 64-bit unknown
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.gen/sources_1/ip/gpll/gpll_stub.vhdl
+-- Design      : gpll
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7a35tcpg236-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gpll is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of gpll : entity is "gpll,clk_wiz_v6_0_19_0_0,{component_name=gpll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
+end gpll;
+
+architecture stub of gpll is
+  attribute syn_black_box : boolean;
+  attribute black_box_pad_pin : string;
+  attribute syn_black_box of stub : architecture is true;
+  attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000..6c4981a
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1011_00,
+         10'b0010_1101_00,
+         10'b0010_0011_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0100_1111_00,
+         10'b0101_1011_00,
+         10'b0111_0111_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_1001_00,
+         10'b1101_0001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_1001_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0111_0001_00,
+         10'b0111_0001_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0110_0001_00,
+         10'b0110_0001_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0101_0110_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0100_1010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000..b662a3e
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,542 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+`ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+`ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+`endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+`ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+`ifdef DEBUG
+      $display("temp: %h", temp);
+`endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_00,
+         10'b0010_1111_00,
+         10'b0010_0111_00,
+         10'b0010_1101_00,
+         10'b0010_0101_00,
+         10'b0010_0101_00,
+         10'b0010_1001_00,
+         10'b0010_1110_00,
+         10'b0010_1110_00,
+         10'b0010_0001_00,
+         10'b0010_0001_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_0110_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1010_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_1100_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0010_0010_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0011_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0011_0111_00,
+         10'b0011_0111_00,
+         10'b0101_1111_00,
+         10'b0111_1111_00,
+         10'b0111_1011_00,
+         10'b1101_0111_00,
+         10'b1110_1011_00,
+         10'b1110_1101_00,
+         10'b1111_1101_00,
+         10'b1111_0111_00,
+         10'b1111_1011_00,
+         10'b1111_1101_00,
+         10'b1111_0011_00,
+         10'b1110_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b1111_0101_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0111_0110_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b0101_1100_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b1100_0001_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0100_0010_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0011_0100_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0010_1000_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0100_1100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00,
+         10'b0010_0100_00
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+`endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+`ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000..154c81f
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,680 @@
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [2559:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b00110_00110_1111101000_1111101001_0000000001,
+         40'b01000_01000_1111101000_1111101001_0000000001,
+         40'b01011_01011_1111101000_1111101001_0000000001,
+         40'b01110_01110_1111101000_1111101001_0000000001,
+         40'b10001_10001_1111101000_1111101001_0000000001,
+         40'b10011_10011_1111101000_1111101001_0000000001,
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide, // Max divide is 64
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [639:0] lookup_low;
+   reg [639:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_0111_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_1101_11,
+         10'b0010_0011_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_0101_11,
+         10'b0010_1001_11,
+         10'b0010_1001_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_1110_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0001_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_0110_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1010_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11,
+         10'b0010_1100_11
+      };
+      
+      lookup_high = {
+         // CP_RES_LFHF
+         10'b0010_1111_11,
+         10'b0010_1111_11,
+         10'b0010_1011_11,
+         10'b0011_1111_11,
+         10'b0100_1111_11,
+         10'b0100_1111_11,
+         10'b0101_1111_11,
+         10'b0110_1111_11,
+         10'b0111_1111_11,
+         10'b0111_1111_11,
+         10'b1100_1111_11,
+         10'b1101_1111_11,
+         10'b1110_1111_11,
+         10'b1111_1111_11,
+         10'b1111_1111_11,
+         10'b1110_0111_11,
+         10'b1110_1011_11,
+         10'b1111_0111_11,
+         10'b1111_1011_11,
+         10'b1111_1011_11,
+         10'b1110_1101_11,
+         10'b1111_1101_11,
+         10'b1111_1101_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1111_0011_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1110_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_0101_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1111_1001_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1110_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1111_1110_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1110_0001_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_0110_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11,
+         10'b1100_1010_11
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000..ff369d1
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,555 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa
+//    Date:             6/15/2015
+//    Design Name:      PLLE3 DRP
+//    Module Name:      plle3_drp_func.h
+//    Version:          1.10
+//    Target Devices:   UltraScale Architecture
+//    Tool versions:    2015.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                         PM_Rise bits have been removed for PLLE3
+// 
+// (c) Copyright 2009-2010, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 64
+   );
+   
+   reg [759:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1  
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001 //19
+         
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 19
+   );
+   
+   reg [639:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0010_1111_01, //1
+         10'b0010_0011_11, //2
+         10'b0011_0011_11, //3
+         10'b0010_0001_11, //4
+         10'b0010_0110_11, //5
+         10'b0010_1010_11, //6
+         10'b0010_1010_11, //7
+         10'b0011_0110_11, //8
+         10'b0010_1100_11, //9
+         10'b0010_1100_11, //10
+         10'b0010_1100_11, //11
+         10'b0010_0010_11, //12
+         10'b0011_1100_11, //13
+         10'b0011_1100_11, //14
+         10'b0011_1100_11, //15
+         10'b0011_1100_11, //16
+         10'b0011_0010_11, //17
+         10'b0011_0010_11, //18
+         10'b0011_0010_11 //19
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+//			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000..fd26211
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,886 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa. Updated by Ralf Krueger
+//    Date:             7/30/2014
+//    Design Name:      MMCME4 DRP
+//    Module Name:      mmcme4_drp_func.h
+//    Version:          1.31
+//    Target Devices:   UltraScale Plus Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for UltraScal+ MMCM.
+//                      
+//	Revision Notes:	3/22 - Updating lookup_low/lookup_high (CR)
+//				4/13 - Fractional divide function in mmcm_frac_count_calc function
+//              2/28/17 - Updated for Ultrascale Plus
+// 
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers.  These should not be modified, they are for development only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+// greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      // of 1 would modify the fractional so that instead of being a .16
+      // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//       is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      // assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [7:0] divide // Max M divide is 128 in UltrascalePlus
+   );
+   
+   reg [5119:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=1 (not allowed)
+         40'b00110_00110_1111101000_1111101001_0000000001,      // M=2
+         40'b01000_01000_1111101000_1111101001_0000000001,      // M=3
+         40'b01011_01011_1111101000_1111101001_0000000001,      // M=4
+         40'b01110_01110_1111101000_1111101001_0000000001,      // M=5
+         40'b10001_10001_1111101000_1111101001_0000000001,      // M=6
+         40'b10011_10011_1111101000_1111101001_0000000001,      // M=7
+         40'b10110_10110_1111101000_1111101001_0000000001,
+         40'b11001_11001_1111101000_1111101001_0000000001,
+         40'b11100_11100_1111101000_1111101001_0000000001,
+         40'b11111_11111_1110000100_1111101001_0000000001,
+         40'b11111_11111_1100111001_1111101001_0000000001,
+         40'b11111_11111_1011101110_1111101001_0000000001,
+         40'b11111_11111_1010111100_1111101001_0000000001,
+         40'b11111_11111_1010001010_1111101001_0000000001,
+         40'b11111_11111_1001110001_1111101001_0000000001,
+         40'b11111_11111_1000111111_1111101001_0000000001,
+         40'b11111_11111_1000100110_1111101001_0000000001,
+         40'b11111_11111_1000001101_1111101001_0000000001,
+         40'b11111_11111_0111110100_1111101001_0000000001,
+         40'b11111_11111_0111011011_1111101001_0000000001,
+         40'b11111_11111_0111000010_1111101001_0000000001,
+         40'b11111_11111_0110101001_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0110010000_1111101001_0000000001,
+         40'b11111_11111_0101110111_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101011110_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0101000101_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100101100_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0100010011_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,                                                                    
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,
+         40'b11111_11111_0011111010_1111101001_0000000001,      // M=127
+         40'b11111_11111_0011111010_1111101001_0000000001       // M=128
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+//  and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [7:0] divide, //  input [7:0] divide // Max M divide is 128 in UltraScalePlus
+      input [8*9:0] BANDWIDTH
+   );
+   
+   reg [1279:0] lookup_low;
+   reg [1279:0] lookup_high;
+   
+   reg [9:0] lookup_entry;
+   
+   begin
+      lookup_low = {
+         // CP_RES_LFHF
+       	10'b0011_1111_11,    // M=1 - not legal
+       	10'b0011_1111_11,    // M=2
+       	10'b0011_1101_11,    // M=3
+       	10'b0011_0101_11,    // M=4
+       	10'b0011_1001_11,    // M=5
+       	10'b0011_1110_11,    // M=6
+       	10'b0011_1110_11,    // M=7
+       	10'b0011_0001_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_0110_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0011_1010_11,
+       	10'b0100_0110_11,
+       	10'b0011_1100_11,
+       	10'b1110_0110_11,
+       	10'b1111_0110_11,
+       	10'b1110_1010_11,
+       	10'b1110_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1111_1010_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1101_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1110_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1111_1100_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1110_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1111_0010_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1100_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1101_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1110_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1111_0100_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11,
+       	10'b1101_1000_11, // M=127
+       	10'b1101_1000_11  // M=128
+};										
+      
+      lookup_high = {
+         // CP_RES_LFHF
+       10'b0111_1111_11,    // M=1 - not legal
+       10'b0111_1111_11,    // M=2
+       10'b1110_1111_11,    // M=3
+       10'b1111_1111_11,    // M=4
+       10'b1111_1011_11,    // M=5
+       10'b1111_1101_11,    // M=6
+       10'b1111_0011_11,    // M=7
+       10'b1110_0101_11,
+       10'b1111_1001_11,
+       10'b1111_1001_11,
+       10'b1110_1110_11,
+       10'b1111_1110_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1111_0001_11,
+       10'b1110_0110_11,
+       10'b1110_0110_11,
+       10'b1111_0110_11,
+       10'b1110_1010_11,
+       10'b1110_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1111_1010_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1101_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1110_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1111_1100_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1110_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1111_0010_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1100_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1101_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1110_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1111_0100_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11,
+       10'b1101_1000_11     // M=128
+};
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      if(BANDWIDTH == "LOW") begin
+         // Low Bandwidth
+         mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+      end else begin
+         // High or optimized bandwidth
+         mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+      end
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1);   //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);    //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0], 
+			pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000..0899943
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,561 @@
+///////////////////////////////////////////////////////////////////////////////
+//    
+//    Company:          AMD
+//    Engineer:         Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+ 
+//    Date:             6/15/2015
+//    Design Name:      PLLE4 DRP
+//    Module Name:      plle4_drp_func.h
+//    Version:          2.0
+//    Target Devices:   UltraScale+ Architecture
+//    Tool versions:    2017.1
+//    Description:      This header provides the functions necessary to  
+//                      calculate the DRP register values for the V6 PLL.
+//                      
+//	Revision Notes:	8/11 - PLLE3 updated for PLLE3 file 4564419
+//	Revision Notes:	6/15 - pll_filter_lookup fixed for max M of 19
+//                           M_Rise bits have been removed for PLLE3
+//	Revision Notes:	2/28/17 - pll_filter_lookup and CPRES updated for 
+//                           Ultrascale+ and for max M of 21
+// 
+// (c) Copyright 2009-2017, 2023 Advanced Micro Devices, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+////////////////////////////////////////////////////////////
+// 
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified.  Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+//    point numbers.  These should not be modified, they are for development 
+//    only
+`define FRAC_PRECISION  10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs 
+//    greater than 32
+`define FIXED_WIDTH     32 
+
+// This function takes a fixed point number and rounds it to the nearest
+//    fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+   (
+      // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+      input [`FIXED_WIDTH:1] decimal,  
+
+      // This describes the precision of the fraction, for example a value
+      //    of 1 would modify the fractional so that instead of being a .16
+      //    fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+      input [`FIXED_WIDTH:1] precision 
+   );
+
+   begin
+   
+   `ifdef DEBUG
+      $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+   `endif
+      // If the fractional precision bit is high then round up
+      if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+         round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+      end else begin
+         round_frac = decimal;
+      end
+   `ifdef DEBUG
+      $display("round_frac: %h", round_frac);
+   `endif
+   end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+//    of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63 
+//    inclusive.  64 should equal 6'b000000 (in other words it is okay to 
+//    ignore the overflow)
+function [13:0] mmcm_pll_divider
+   (
+      input [7:0] divide,        // Max divide is 128
+      input [31:0] duty_cycle    // Duty cycle is multiplied by 100,000
+   );
+
+   reg [`FIXED_WIDTH:1]    duty_cycle_fix;
+   
+   // High/Low time is initially calculated with a wider integer to prevent a
+   // calculation error when it overflows to 64.
+   reg [6:0]               high_time;
+   reg [6:0]               low_time;
+   reg                     w_edge;
+   reg                     no_count;
+
+   reg [`FIXED_WIDTH:1]    temp;
+
+   begin
+      // Duty Cycle must be between 0 and 1,000
+      if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+         $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+   `endif
+         $finish;
+      end
+
+      // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+      duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+      
+   `ifdef DEBUG
+      $display("duty_cycle_fix: %h", duty_cycle_fix);
+   `endif
+
+      // If the divide is 1 nothing needs to be set except the no_count bit.
+      //    Other values are dummies
+      if(divide == 7'h01) begin
+         high_time   = 7'h01;
+         w_edge      = 1'b0;
+         low_time    = 7'h01;
+         no_count    = 1'b1;
+      end else begin
+         temp = round_frac(duty_cycle_fix*divide, 1);
+
+         // comes from above round_frac
+         high_time   = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1]; 
+         // If the duty cycle * divide rounded is .5 or greater then this bit
+         //    is set.
+         w_edge      = temp[`FRAC_PRECISION]; // comes from round_frac
+         
+         // If the high time comes out to 0, it needs to be set to at least 1
+         // and w_edge set to 0
+         if(high_time == 7'h00) begin
+            high_time   = 7'h01;
+            w_edge      = 1'b0;
+         end
+
+         if(high_time == divide) begin
+            high_time   = divide - 1;
+            w_edge      = 1'b1;
+         end
+         
+         // Calculate low_time based on the divide setting and set no_count to
+         //    0 as it is only used when divide is 1.
+         low_time    = divide - high_time; 
+         no_count    = 1'b0;
+      end
+
+      // Set the return value.
+      mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+   end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux 
+//  of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+//    is used.
+function [10:0] mmcm_pll_phase
+   (
+      // divide must be an integer (use fractional if not)
+      //  assumed that divide already checked to be valid
+      input [7:0] divide, // Max divide is 128
+
+      // Phase is given in degrees (-360,000 to 360,000)
+      input signed [31:0] phase
+   );
+
+   reg [`FIXED_WIDTH:1] phase_in_cycles;
+   reg [`FIXED_WIDTH:1] phase_fixed;
+   reg [1:0]            mx;
+   reg [5:0]            delay_time;
+   reg [2:0]            phase_mux;
+
+   reg [`FIXED_WIDTH:1] temp;
+
+   begin
+`ifdef DEBUG
+      $display("pll_phase-divide:%d,phase:%d",
+         divide, phase);
+`endif
+   
+      if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+         $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+         $finish;
+      end
+
+      // If phase is less than 0, convert it to a positive phase shift
+      // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+      if(phase < 0) begin
+         phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+      end else begin
+         phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+      end
+
+      // Put phase in terms of decimal number of vco clock cycles
+      phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+      $display("phase_in_cycles: %h", phase_in_cycles);
+`endif  
+      
+
+	 temp  =  round_frac(phase_in_cycles, 3);
+
+	 // set mx to 2'b00 that the phase mux from the VCO is enabled
+	 mx    			=  2'b00; 
+	 phase_mux      =  temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+	 delay_time     =  temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+      
+   `ifdef DEBUG
+      $display("temp: %h", temp);
+   `endif
+
+      // Setup the return value
+      mmcm_pll_phase={mx, phase_mux, delay_time};
+   end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [839:0]   lookup;
+   
+   begin
+      lookup = {
+         // This table is composed of:
+         // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+         40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+         40'b00110_00110_1111101000_1111101001_0000000001, //2
+         40'b01000_01000_1111101000_1111101001_0000000001, //3
+         40'b01011_01011_1111101000_1111101001_0000000001, //4
+         40'b01110_01110_1111101000_1111101001_0000000001, //5
+         40'b10001_10001_1111101000_1111101001_0000000001, //6
+         40'b10011_10011_1111101000_1111101001_0000000001, //7
+         40'b10110_10110_1111101000_1111101001_0000000001, //8
+         40'b11001_11001_1111101000_1111101001_0000000001, //9
+         40'b11100_11100_1111101000_1111101001_0000000001, //10
+         40'b11111_11111_1110000100_1111101001_0000000001, //11
+         40'b11111_11111_1100111001_1111101001_0000000001, //12
+         40'b11111_11111_1011101110_1111101001_0000000001, //13
+         40'b11111_11111_1010111100_1111101001_0000000001, //14
+         40'b11111_11111_1010001010_1111101001_0000000001, //15
+         40'b11111_11111_1001110001_1111101001_0000000001, //16
+         40'b11111_11111_1000111111_1111101001_0000000001, //17
+         40'b11111_11111_1000100110_1111101001_0000000001, //18
+         40'b11111_11111_1000001101_1111101001_0000000001, //19
+         40'b11111_11111_0111110100_1111101001_0000000001, //20
+         40'b11111_11111_0111011011_1111101001_0000000001  //21
+      };
+      
+      // Set lookup_entry with the explicit bits from lookup with a part select
+      mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+   `ifdef DEBUG
+      $display("lock_lookup: %b", pll_lock_lookup);
+   `endif
+   end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+//  and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+   (
+      input [6:0] divide // Max divide is 21
+   );
+   
+   reg [209:0] lookup;
+   reg [9:0] lookup_entry;
+   
+   begin
+
+      lookup = {
+         // CP_RES_LFHF
+         10'b0011_0111_11, //1  not legal in Ultrascale+
+         10'b0011_0111_11, //2
+         10'b0011_0011_11, //3
+         10'b0011_1001_11, //4
+         10'b0011_0001_11, //5
+         10'b0100_1110_11, //6
+         10'b0011_0110_11, //7
+         10'b0011_1010_11, //8
+         10'b0111_1001_11, //9
+         10'b0111_1001_11, //10
+         10'b0101_0110_11, //11
+         10'b1100_0101_11, //12
+         10'b0101_1010_11, //13
+         10'b0110_0110_11, //14
+         10'b0110_1010_11, //15
+         10'b0111_0110_11, //16
+         10'b1111_0101_11, //17
+         10'b1100_0110_11, //18
+         10'b1110_0001_11, //19
+         10'b1101_0110_11, //20
+         10'b1111_0001_11  //21
+      };
+      
+         mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+      
+   `ifdef DEBUG
+      $display("filter_lookup: %b", pll_filter_lookup);
+   `endif
+   end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" 
+// will need to divide the doubled clock VCO clock frequency by 
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will 
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+   (
+      input [8*9:0] CLKOUTPHY_MODE
+   );
+
+      if(CLKOUTPHY_MODE == "VCO_X2") begin
+         mmcm_pll_clkoutphy_calc= 2'b00;
+      end else if(CLKOUTPHY_MODE == "VCO") begin
+         mmcm_pll_clkoutphy_calc= 2'b01;
+      end else if(CLKOUTPHY_MODE == "CLKIN") begin
+         mmcm_pll_clkoutphy_calc= 2'b11;
+      end else begin // Assume "VCO_HALF"
+         mmcm_pll_clkoutphy_calc= 2'b10;
+      end
+      
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle // Multiplied by 100,000
+   );
+   
+   reg [13:0] div_calc;
+   reg [16:0] phase_calc;
+   
+   begin
+   `ifdef DEBUG
+      $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+         divide, phase, duty_cycle);
+   `endif
+   
+      // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+      div_calc = mmcm_pll_divider(divide, duty_cycle);
+      // mx[10:9], pm[8:6], dt[5:0]
+      phase_calc = mmcm_pll_phase(divide, phase);
+
+      // Return value is the upper and lower address of counter
+      //    Upper address is:
+      //       RESERVED    [31:26]
+      //       MX          [25:24]
+      //       EDGE        [23]
+      //       NOCOUNT     [22]
+      //       DELAY_TIME  [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX   [15:13]
+      //       RESERVED    [12]
+      //       HIGH_TIME   [11:6]
+      //       LOW_TIME    [5:0]
+      
+   `ifdef DEBUG
+      $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+         divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0], 
+         div_calc[13], div_calc[12], 
+         phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+   `endif
+      
+      mmcm_pll_count_calc =
+         {
+            // Upper Address
+            6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0], 
+            // Lower Address
+            phase_calc[8:6], 1'b0, div_calc[11:0]
+         };
+   end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+// 
+function [37:0] mmcm_pll_frac_count_calc
+   (
+      input [7:0] divide, // Max divide is 128
+      input signed [31:0] phase,
+      input [31:0] duty_cycle, // Multiplied by 1,000
+      input [9:0] frac // Multiplied by 1000
+   );
+   
+	//Required for fractional divide calculations
+			  reg	[7:0]			lt_frac;
+			  reg	[7:0]			ht_frac;
+			
+			  reg	/*[7:0]*/			wf_fall_frac;
+			  reg	/*[7:0]*/			wf_rise_frac;
+
+			  reg [31:0] a;
+			  reg	[7:0]			pm_rise_frac_filtered ;
+			  reg	[7:0]			pm_fall_frac_filtered ;	
+			  reg [7:0]			clkout0_divide_int;
+			  reg [2:0]			clkout0_divide_frac;
+			  reg	[7:0]			even_part_high;
+			  reg	[7:0]			even_part_low;
+
+			  reg	[7:0]			odd;
+			  reg	[7:0]			odd_and_frac;
+
+			  reg	[7:0]			pm_fall;
+			  reg	[7:0]			pm_rise;
+			  reg	[7:0]			dt;
+			  reg	[7:0]			dt_int; 
+			  reg [63:0]		dt_calc;
+
+			  reg	[7:0]			pm_rise_frac; 
+			  reg	[7:0]			pm_fall_frac;
+	 
+			  reg [31:0] a_per_in_octets;
+			  reg [31:0] a_phase_in_cycles;
+
+				parameter precision = 0.125;
+
+			  reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+			  reg [31: 0] phase_pos;
+			  reg [31: 0] phase_vco;
+			  reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+			  reg [13:0] div_calc;
+			  reg [16:0] phase_calc;
+
+   begin
+	`ifdef DEBUG
+			$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+				divide, phase, duty_cycle);
+	`endif
+   
+   //convert phase to fixed
+   if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+      $display("ERROR: phase of $phase is not between -360000 and 360000");
+	`endif
+      $finish;
+   end
+
+
+      // Return value is
+      //    Transfer data
+      //       RESERVED     [37:36]
+      //       FRAC_TIME    [35:33]
+      //       FRAC_WF_FALL [32]
+      //    Upper address is:
+      //       RESERVED     [31:26]
+      //       MX           [25:24]
+      //       EDGE         [23]
+      //       NOCOUNT      [22]
+      //       DELAY_TIME   [21:16]
+      //    Lower Address is:
+      //       PHASE_MUX    [15:13]
+      //       RESERVED     [12]
+      //       HIGH_TIME    [11:6]
+      //       LOW_TIME     [5:0]
+      
+      
+
+	clkout0_divide_frac = frac / 125;
+	clkout0_divide_int = divide;
+
+	even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+	even_part_low = even_part_high;
+									
+	odd = clkout0_divide_int - even_part_high - even_part_low;
+	odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+	lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+	ht_frac = even_part_low  - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+	pm_fall =  {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2 
+	pm_rise = 0; //0
+    
+	wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+	wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+	//Calculate phase in fractional cycles
+	a_per_in_octets		= (8 * divide) + (frac / 125) ;
+	a_phase_in_cycles	= (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+	pm_rise_frac		= (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+	dt_calc 	= ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+	dt 	= dt_calc[7:0];
+
+	pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ;				//((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+	dt_int			= dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+	pm_fall_frac		= pm_fall + pm_rise_frac;
+	pm_fall_frac_filtered	= pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+	div_calc	= mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+	phase_calc	= mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+		
+      mmcm_pll_frac_count_calc[37:0] =
+         {		2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+			1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0], 
+			3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+		} ;
+
+   `ifdef DEBUG
+      $display("-%d.%d p%d>>  :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+   `endif
+
+   end
+endfunction
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/compile.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/compile.do
new file mode 100644
index 0000000..6fb6624
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/compile.do
@@ -0,0 +1,15 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xil_defaultlib -64 -incr -mfcu  "+incdir+../../../ipstatic" "+incdir+../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/gpll.sh
new file mode 100755
index 0000000..30917bb
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/gpll.sh
@@ -0,0 +1,335 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : Siemens ModelSim Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+#                using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+#                command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+#                switch with the directory path where the library is created while generating the script
+#                with export_simulation.
+#
+#                Alternatively, you can set the library path by setting the following project property:-
+#
+#                 set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+#                You can also point to the simulation library by either setting the 'lib_map_path' global
+#                variable in this script or specify it with the '-lib_map_path' switch while executing this
+#                script (type 'gpll.sh -help' for more information).
+#
+#                Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+#                generated script, but if design is targetted for system simulation containing SystemC/C++/C
+#                sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+#                For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# simulation root library directory
+sim_lib_dir="modelsim_lib"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim  -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous simulator index file
+    true
+  else
+    # copy simulator index file to current directory
+    copy_setup_file
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    ref_lib_dir=$lib_map_path
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # do not recreate design library directories
+    true
+  else
+    # create design library directories
+    create_lib_dir
+  fi
+}
+
+# copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+  fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+  mkdir $lib_dir
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.Vivado_Implementation.queue.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/gpll.udo
index e69de29..e69de29 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.Vivado_Implementation.queue.rst
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/gpll.udo
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/simulate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/simulate.do
new file mode 100644
index 0000000..d96bb05
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc"  -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.gpll xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {gpll.udo}
+
+run 1000ns
+
+quit -force
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/wave.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/wave.do
new file mode 100644
index 0000000..1e0a9a4
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/modelsim/wave.do
@@ -0,0 +1,2 @@
+if { [catch {[add wave *]}] } {}
+add wave /glbl/GSR
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/compile.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/compile.do
new file mode 100644
index 0000000..0c0ef1e
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/compile.do
@@ -0,0 +1,15 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xil_defaultlib -64 -incr -mfcu  "+incdir+../../../ipstatic" "+incdir+../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/elaborate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/elaborate.do
new file mode 100644
index 0000000..75f4175
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 -l elaborate.log +acc=npr -suppress 10016  -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.gpll xil_defaultlib.glbl -o gpll_opt
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/gpll.sh
new file mode 100755
index 0000000..822cfdf
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/gpll.sh
@@ -0,0 +1,347 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : Siemens Questa Advanced Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+#                using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+#                command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+#                switch with the directory path where the library is created while generating the script
+#                with export_simulation.
+#
+#                Alternatively, you can set the library path by setting the following project property:-
+#
+#                 set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+#                You can also point to the simulation library by either setting the 'lib_map_path' global
+#                variable in this script or specify it with the '-lib_map_path' switch while executing this
+#                script (type 'gpll.sh -help' for more information).
+#
+#                Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+#                generated script, but if design is targetted for system simulation containing SystemC/C++/C
+#                sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+#                For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+export SIM_VER_QUESTA=
+export GCC_VER_QUESTA=
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# simulation root library directory
+sim_lib_dir="questa_lib"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "elaborate" )
+       elaborate
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    elaborate
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee  elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64  -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous simulator index file
+    true
+  else
+    # copy simulator index file to current directory
+    copy_setup_file
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    ref_lib_dir=$lib_map_path
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # do not recreate design library directories
+    true
+  else
+    # create design library directories
+    create_lib_dir
+  fi
+}
+
+# copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+  fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+  mkdir $lib_dir
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.init_design.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/gpll.udo
index e69de29..e69de29 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.init_design.end.rst
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/gpll.udo
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/simulate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/simulate.do
new file mode 100644
index 0000000..caf90c3
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim  -lib xil_defaultlib gpll_opt
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {gpll.udo}
+
+run 1000ns
+
+quit -force
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/wave.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/wave.do
new file mode 100644
index 0000000..1e0a9a4
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/questa/wave.do
@@ -0,0 +1,2 @@
+if { [catch {[add wave *]}] } {}
+add wave /glbl/GSR
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/compile.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/compile.do
new file mode 100644
index 0000000..aa112b6
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/compile.do
@@ -0,0 +1,18 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+vlib work
+vlib riviera/xil_defaultlib
+
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xil_defaultlib  -incr -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" -l xil_defaultlib \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/gpll.sh
new file mode 100755
index 0000000..67f662b
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/gpll.sh
@@ -0,0 +1,314 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : Aldec Riviera-PRO Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+#                using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+#                command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+#                switch with the directory path where the library is created while generating the script
+#                with export_simulation.
+#
+#                Alternatively, you can set the library path by setting the following project property:-
+#
+#                 set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+#                You can also point to the simulation library by either setting the 'lib_map_path' global
+#                variable in this script or specify it with the '-lib_map_path' switch while executing this
+#                script (type 'gpll.sh -help' for more information).
+#
+#                Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+#                generated script, but if design is targetted for system simulation containing SystemC/C++/C
+#                sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+#                For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+export SIM_VER_RIVIERA=
+export GCC_VER_RIVIERA=
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# simulation root library directory
+sim_lib_dir="riviera"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous design library mappings
+    true
+  else
+    # map simulator index file
+    map_setup_file
+  fi
+}
+
+# map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.opt_design.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/gpll.udo
index e69de29..e69de29 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.opt_design.end.rst
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/gpll.udo
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/simulate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/simulate.do
new file mode 100644
index 0000000..f6eedad
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/riviera/simulate.do
@@ -0,0 +1,14 @@
+transcript off
+onbreak {quit -force}
+onerror {quit -force}
+transcript on
+
+asim +access +r +m+gpll  -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.gpll xil_defaultlib.glbl
+
+do {gpll.udo}
+
+run 1000ns
+
+endsim
+
+quit -force
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/gpll.sh
new file mode 100755
index 0000000..bb6e422
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/gpll.sh
@@ -0,0 +1,386 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : Synopsys Verilog Compiler Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+#                using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+#                command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+#                switch with the directory path where the library is created while generating the script
+#                with export_simulation.
+#
+#                Alternatively, you can set the library path by setting the following project property:-
+#
+#                 set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+#                You can also point to the simulation library by either setting the 'lib_map_path' global
+#                variable in this script or specify it with the '-lib_map_path' switch while executing this
+#                script (type 'gpll.sh -help' for more information).
+#
+#                Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+#                generated script, but if design is targetted for system simulation containing SystemC/C++/C
+#                sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+#                For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+export SIM_VER_VCS=
+export GCC_VER_VCS=
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# set vhdlan compile options
+vhdlan_opts="-full64 -l .tmp_log"
+
+# set vlogan compile options
+vlogan_opts="-full64 -l .tmp_log"
+
+# set vcs elaboration options
+vcs_elab_opts="-full64 -debug_acc -t ps -licqueue -l elaborate.log"
+
+# set vcs simulation options
+vcs_sim_opts="-ucli -licqueue -l simulate.log "
+
+# set design libraries
+design_libs=(xil_defaultlib)
+
+# simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "elaborate" )
+       elaborate
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    elaborate
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../ipstatic" +incdir+"../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" \
+  "../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+  "../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+  2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+  glbl.v \
+  2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.gpll xil_defaultlib.glbl -o gpll_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./gpll_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous design library mappings
+    true
+  else
+    # define design library mappings
+    create_lib_mappings
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # do not recreate design library directories
+    true
+  else
+    # create design library directories
+    create_lib_dir
+  fi
+}
+
+# define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($lib_map_path == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+
+  echo "LIBRARY_SCAN=TRUE" >> $file
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# create design library directory
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key gpll_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc gpll_simv.daidir vcs_lib c.obj)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/simulate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/simulate.do
new file mode 100644
index 0000000..b77c6f1
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/vcs/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+quit
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/gpll.sh
new file mode 100755
index 0000000..4505ed4
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/gpll.sh
@@ -0,0 +1,390 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : Cadence Xcelium Parallel Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
+#                using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
+#                command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
+#                switch with the directory path where the library is created while generating the script
+#                with export_simulation.
+#
+#                Alternatively, you can set the library path by setting the following project property:-
+#
+#                 set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
+#
+#                You can also point to the simulation library by either setting the 'lib_map_path' global
+#                variable in this script or specify it with the '-lib_map_path' switch while executing this
+#                script (type 'gpll.sh -help' for more information).
+#
+#                Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
+#                generated script, but if design is targetted for system simulation containing SystemC/C++/C
+#                sources, then the library path MUST be specified upfront when calling export_simulation.
+#
+#                For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#**********************************************************************************************************
+export SIM_VER_XCELIUM=
+export GCC_VER_XCELIUM=
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# set xmvhdl compile options
+xmvhdl_opts="-64bit -messages -relax -logfile .tmp_log -update"
+
+# set xmvlog compile options
+xmvlog_opts="-64bit -messages -logfile .tmp_log -update"
+
+# set xmelab elaboration options
+xmelab_opts="-64bit -relax -access +r -namemap_mixgen -messages -logfile elaborate.log"
+
+# set xmsim simulation options
+xmsim_opts="-64bit -logfile simulate.log"
+
+# set design libraries for elaboration
+design_libs_elab="-libname xil_defaultlib -libname unisims_ver -libname unimacro_ver -libname secureip"
+
+# set design libraries
+design_libs=(simprims_ver xil_defaultlib)
+
+# simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "elaborate" )
+       elaborate
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    elaborate
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  xmvlog -work xil_defaultlib $xmvlog_opts +incdir+"../../../ipstatic" +incdir+"../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" \
+  "../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+  "../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+  2>&1 | tee compile.log; cat .tmp_log > xmvlog.log 2>/dev/null
+
+  xmvlog -work xil_defaultlib $xmvlog_opts \
+  glbl.v \
+  2>&1 | tee -a compile.log; cat .tmp_log >> xmvlog.log 2>/dev/null
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xmelab $xmelab_opts $design_libs_elab xil_defaultlib.gpll xil_defaultlib.glbl
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xmsim $xmsim_opts xil_defaultlib.gpll -input simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous design library mappings
+    true
+  else
+    # define design library mappings
+    create_lib_mappings
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # do not recreate design library directories
+    true
+  else
+    # create design library directories
+    create_lib_dir
+  fi
+}
+
+# define design library mappings
+create_lib_mappings()
+{
+  file="hdl.var"
+  touch $file
+
+  file="cds.lib"
+  if [[ -e $file ]]; then
+    if [[ ($lib_map_path == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($lib_map_path != "") && !(-e $lib_map_path) ]]; then
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="INCLUDE $lib_map_path/cds.lib"
+    echo $incl_ref >> $file
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="DEFINE $lib $sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+}
+
+# create design library directory
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log gpll_sc.so .tmp_log xcelium_lib waves.shm c.obj)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(xmvlog.log xmvhdl.log xmsc.log compile.log elaborate.log simulate.log diag_report.log xsc_report.log .tmp_log)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.phys_opt_design.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/hdl.var
index e69de29..e69de29 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.phys_opt_design.end.rst
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/hdl.var
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/simulate.do b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/simulate.do
new file mode 100644
index 0000000..baf3d48
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xcelium/simulate.do
@@ -0,0 +1,7 @@
+set pack_assert_off {numeric_std std_logic_arith}
+
+database -open waves -into waves.shm -default
+catch {probe -create -shm -all -variables -depth 1} msg
+
+run 1000ns
+exit
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/README.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/README.txt
new file mode 100644
index 0000000..f9a64c5
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/README.txt
@@ -0,0 +1,50 @@
+################################################################################
+# Vivado (TM) v2026.1 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and how to fetch design source file details
+#             from the file_info.txt file.
+#
+# Generated by export_simulation on Fri Sep 25 22:22:19 UTC 2026
+#
+################################################################################
+
+1. Steps to run the generated simulation script
+
+From the shell prompt in the current directory, issue the following command:-
+
+./gpll.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first calls the 'check_args' function, the purpose of which
+is to verify the generated script arguments and print error if incorrect switch
+is specified. The 'run' function then calls the 'setup' function, the purpose of
+which is to specify custom or initialization commands. The function also executes
+following sub-functions:-
+'reset_run' if -reset_run switch is specified.
+'reset_log' if -reset_log switch is specified.
+
+The purpose of 'reset_run' function' is to delete the simulator generated design
+data from the previous run and the purpose of 'reset_log' function' is to delete
+the simulator generated log files.
+
+The 'run' function then calls the 'init_lib' function, the purpose of which is to
+create design library mappings and directories. This function is called before the
+'compile' step. By default, if '-step' switch is specified with the script then the
+script will execute that specfic step, else it will execute all steps applicable
+for the target simulator.
+
+For more information on the script, please type './gpll.sh -help'
+
+2. Design source file information
+
+export_simulation generates a 'file_info.txt' file that contains design file information
+based on the compile order when export_simulation was executed from Vivado. The file
+contains information about the file name, type, library it is compiled into, whether
+it is part of the IP, associated library, file path information in a comma separated
+format. This file can be parsed to extract the required information for generating a
+custom script or can be read from verification test infra.
+
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/cmd.tcl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/cmd.tcl
new file mode 100644
index 0000000..6ac0dc8
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns
+quit
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/file_info.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/file_info.txt
new file mode 100644
index 0000000..99aafb9
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/file_info.txt
@@ -0,0 +1,3 @@
+gpll_clk_wiz.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+gpll.v,verilog,xil_defaultlib,../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v,incdir="../../../ipstatic"incdir="../../../../../../../../../../../vivado/2026.1/data/rsb/busdef"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/glbl.v b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/glbl.v
new file mode 100644
index 0000000..ed3b249
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/gpll.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/gpll.sh
new file mode 100755
index 0000000..b0d79ca
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/gpll.sh
@@ -0,0 +1,387 @@
+#!/bin/bash -f
+#**********************************************************************************************************
+# Vivado (TM) v2026.1 (64-bit)
+#
+# Script generated by Vivado on Fri Sep 25 22:22:19 UTC 2026
+# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+# Filename     : gpll.sh
+# Simulator    : AMD Vivado Simulator
+# Description  : Simulation script generated by export_simulation Tcl command
+# Purpose      : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
+#                design. The script will copy the library mapping file from the compiled library directory,
+#                create design library directories and library mappings in the mapping file.
+#
+# Usage        : gpll.sh
+#                gpll.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
+#                gpll.sh [-rerun]
+#                gpll.sh [-reset_run]
+#                gpll.sh [-clean]
+#                gpll.sh [-reset_log]
+#                gpll.sh [-help]
+#
+#               * The -noclean_files switch is deprecated and will not peform any function (by default, the
+#                 simulator generated files will not be removed unless -reset_run switch is used)
+#
+#**********************************************************************************************************
+export SIM_VER_XSIM=
+export GCC_VER_XSIM=
+
+# catch pipeline exit status
+set -Eeuo pipefail
+
+# resolve compiled library path in xsim.ini
+export RDI_DATADIR="/home/imar/vivado/2026.1/data"
+
+# set xvlog options
+xvlog_opts="--incr --relax "
+
+# simulation root library directory
+sim_lib_dir="xsim.dir"
+
+# script info
+echo -e "gpll.sh - Script generated by export_simulation (Vivado v2026.1 (64-bit)-id)\n"
+
+# main steps
+run()
+{
+  check_args $*
+  setup
+  if [[ ($b_step == 1) ]]; then
+    case $step in
+      "compile" )
+       init_lib
+       compile
+      ;;
+      "elaborate" )
+       elaborate
+      ;;
+      "simulate" )
+       simulate
+      ;;
+      * )
+        echo -e "ERROR: Invalid or missing step '$step' (type \"./gpll.sh -help\" for more information)\n"
+        exit 1
+      esac
+  else
+    init_lib
+    compile
+    elaborate
+    simulate
+  fi
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --incr --debug typical --relax --mt 8  -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot gpll xil_defaultlib.gpll xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim gpll -key {Behavioral:sim_1:Functional:gpll} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  # delete previous files for a clean rerun
+  if [[ ($b_reset_run == 1) ]]; then
+    reset_run
+    echo -e "INFO: Simulation run files deleted.\n"
+    exit 0
+  fi
+
+  # delete previous design library generated data
+  if [[ ($b_clean == 1) ]]; then
+    clean
+    echo -e "INFO: Design library generated data deleted.\n"
+    exit 0
+  fi
+
+  # delete previous log files
+  if [[ ($b_reset_log == 1) ]]; then
+    reset_log
+    echo -e "INFO: Simulation run log files deleted.\n"
+    exit 0
+  fi
+
+  # add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# simulator index file/library directory processing
+init_lib()
+{
+  if [[ ($b_rerun == 1) ]]; then
+    # keep previous state for incremental run
+    return 0
+  fi
+
+  if [[ ($b_keep_index == 1) ]]; then
+    # keep previous simulator index file
+    true
+  else
+    # copy simulator index file to current directory
+    copy_setup_file
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    ref_lib_dir=$lib_map_path
+  fi
+}
+
+# copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+
+  if [[ ($lib_map_path == "") ]]; then
+    lib_map_path="/home/imar/vivado/2026.1/data/xsim"
+  fi
+
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # map local design libraries to xsim.ini
+    map_local_libs
+  fi
+}
+
+# map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # local design libraries
+  local_libs=(xil_defaultlib)
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+
+    # create a backup copy of the xsim.ini file
+    cp $file $file_backup
+
+    # read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+
+      # split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+
+      # if local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+
+      # add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+
+    # append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+
+      if [[ (${#local_mappings[@]} -eq 0) ]] ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      elif `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+
+    # write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb gpll.wdb xsim.dir libdpi.so)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# delete generated design library data from the previous run
+clean()
+{
+  files_to_remove=("${design_libs[@]}")
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="$sim_lib_dir/${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  # delete design library directory
+  rm -rf $sim_lib_dir
+}
+
+# delete generated log files from the previous run
+reset_log()
+{
+  files_to_remove=(xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# check switch argument value
+check_arg_value()
+{
+  if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
+    echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
+    echo -e "ERROR: Simulation library directory path not specified (type \"./gpll.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# check command line arguments
+check_args()
+{
+  arg_count=$#
+  if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
+    usage
+  fi
+  while [[ "$#" -gt 0 ]]; do
+    case $1 in
+      -step)          check_arg_value $1 $2;step=$2;         b_step=1;         shift;;
+      -lib_map_path)  check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
+      -gen_bypass)    b_gen_bypass=1    ;;
+      -rerun)         b_rerun=1         ;;
+      -reset_run)     b_reset_run=1     ;;
+      -clean)         b_clean=1         ;;
+      -reset_log)     b_reset_log=1     ;;
+      -keep_index)    b_keep_index=1    ;;
+      -noclean_files) b_noclean_files=1 ;;
+      -help|-h)       ;;
+      *) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
+    esac
+     shift
+  done
+
+  # -reset_run is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
+    echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -clean is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_clean == 1) ]]; then
+    echo -e "ERROR: -clean switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -reset_log is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
+    echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -keep_index is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
+    echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  # -noclean_files is not applicable with other switches
+  if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
+    echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
+    exit 1
+  fi
+}
+
+# script usage
+usage()
+{
+  msg="Usage: gpll.sh [-help]\n\
+Usage: gpll.sh [-step]\n\
+Usage: gpll.sh [-lib_map_path]\n\
+Usage: gpll.sh [-rerun]\n\
+Usage: gpll.sh [-reset_run]\n\
+Usage: gpll.sh [-clean]\n\
+Usage: gpll.sh [-reset_log]\n\
+Usage: gpll.sh [-keep_index]\n\
+Usage: gpll.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-rerun] -- Rerun step(s) in incremental mode (data generated from the previous run will be retained).\n\
+To rerun a specific step, pass the -step <name> switch in addition to -rerun switch.\n\n\
+[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
+file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
+NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
+NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
+[-clean] -- Delete simulator generated design library data from the previous run. This switch will not\n\
+execute steps defined in the script.\n\n\
+[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
+[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
+  echo -e $msg
+  exit 0
+}
+
+# initialize globals
+step=""
+lib_map_path=""
+b_step=0
+b_lib_map_path=0
+b_gen_bypass=0
+b_rerun=0
+b_reset_run=0
+b_clean=0
+b_reset_log=0
+b_keep_index=0
+b_noclean_files=0
+
+# launch script
+run $*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/vlog.prj b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/vlog.prj
new file mode 100644
index 0000000..1a5b165
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.ip_user_files/sim_scripts/gpll/xsim/vlog.prj
@@ -0,0 +1,8 @@
+verilog xil_defaultlib -i "../../../../../../../../../../../vivado/2026.1/data/rsb/busdef" --include "../../../ipstatic" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll_clk_wiz.v" \
+"../../../../AT-0000LI02.gen/sources_1/ip/gpll/gpll.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_1.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_1.xml
deleted file mode 100644
index df649ff..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_1.xml
+++ /dev/null
@@ -1,16 +0,0 @@
-<?xml version="1.0"?>
-<Runs Version="1" Minor="0">
-	<Run Id="synth_1" LaunchDir="/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
-	<Run Id="impl_1" LaunchDir="/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
-		<Parent Id="synth_1"/>
-	</Run>
-	<Parameters>
-		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
-		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
-		<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
-		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
-		<Parameter Name="general.usePosixSpawnForFork" Val="true" Type="bool"/>
-	</Parameters>
-	<ProductInfo Name="vivado"/>
-</Runs>
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_2.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_2.xml
deleted file mode 100644
index df649ff..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/.jobs/vrs_config_2.xml
+++ /dev/null
@@ -1,16 +0,0 @@
-<?xml version="1.0"?>
-<Runs Version="1" Minor="0">
-	<Run Id="synth_1" LaunchDir="/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
-	<Run Id="impl_1" LaunchDir="/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
-		<Parent Id="synth_1"/>
-	</Run>
-	<Parameters>
-		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
-		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
-		<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
-		<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
-		<Parameter Name="general.usePosixSpawnForFork" Val="true" Type="bool"/>
-	</Parameters>
-	<ProductInfo Name="vivado"/>
-</Runs>
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.init_design.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.init_design.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.init_design.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.opt_design.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.opt_design.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.opt_design.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.phys_opt_design.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.phys_opt_design.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.phys_opt_design.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.end.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.place_design.end.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.end.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.route_design.end.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.begin.rst
deleted file mode 100644
index 05136e9..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.begin.rst
+++ /dev/null
@@ -1,10 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="imar" Host="IRON-B" Pid="285660" HostCore="4" HostMemory="7980808">
-    </Process>
-</ProcessHandle>
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="imar" Host="IRON-B" Pid="287663" HostCore="4" HostMemory="7980808">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.end.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.vivado.end.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.begin.rst
deleted file mode 100644
index 85113b5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command=".planAhead." Owner="imar" Host="" Pid="287718">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.end.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/.write_bitstream.end.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.js b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.js
deleted file mode 100755
index 61806d0..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.js
+++ /dev/null
@@ -1,270 +0,0 @@
-//
-//  Vivado(TM)
-//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
-//  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
-//  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
-//
-
-// GLOBAL VARIABLES
-var ISEShell = new ActiveXObject( "WScript.Shell" );
-var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
-var ISERunDir = "";
-var ISELogFile = "runme.log";
-var ISELogFileStr = null;
-var ISELogEcho = true;
-var ISEOldVersionWSH = false;
-
-
-
-// BOOTSTRAP
-ISEInit();
-
-
-
-//
-// ISE FUNCTIONS
-//
-function ISEInit() {
-
-  // 1. RUN DIR setup
-  var ISEScrFP = WScript.ScriptFullName;
-  var ISEScrN = WScript.ScriptName;
-  ISERunDir = 
-    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
-
-  // 2. LOG file setup
-  ISELogFileStr = ISEOpenFile( ISELogFile );
-
-  // 3. LOG echo?
-  var ISEScriptArgs = WScript.Arguments;
-  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
-    if ( ISEScriptArgs(loopi) == "-quiet" ) {
-      ISELogEcho = false;
-      break;
-    }
-  }
-
-  // 4. WSH version check
-  var ISEOptimalVersionWSH = 5.6;
-  var ISECurrentVersionWSH = WScript.Version;
-  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
-
-    ISEStdErr( "" );
-    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
-	       ISEOptimalVersionWSH + " or higher. Downloads" );
-    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
-    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
-    ISEStdErr( "" );
-
-    ISEOldVersionWSH = true;
-  }
-
-}
-
-function ISEStep( ISEProg, ISEArgs ) {
-
-  // CHECK for a STOP FILE
-  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
-    ISEStdErr( "" );
-    ISEStdErr( "*** Halting run - EA reset detected ***" );
-    ISEStdErr( "" );
-    WScript.Quit( 1 );
-  }
-
-  // WRITE STEP HEADER to LOG
-  ISEStdOut( "" );
-  ISEStdOut( "*** Running " + ISEProg );
-  ISEStdOut( "    with args " + ISEArgs );
-  ISEStdOut( "" );
-
-  // LAUNCH!
-  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
-  if ( ISEExitCode != 0 ) {
-    WScript.Quit( ISEExitCode );
-  }
-
-}
-
-function ISEExec( ISEProg, ISEArgs ) {
-
-  var ISEStep = ISEProg;
-  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
-    ISEProg += ".bat";
-  }
-
-  var ISECmdLine = ISEProg + " " + ISEArgs;
-  var ISEExitCode = 1;
-
-  if ( ISEOldVersionWSH ) { // WSH 5.1
-
-    // BEGIN file creation
-    ISETouchFile( ISEStep, "begin" );
-
-    // LAUNCH!
-    ISELogFileStr.Close();
-    ISECmdLine = 
-      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
-    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
-    ISELogFileStr = ISEOpenFile( ISELogFile );
-
-  } else {  // WSH 5.6
-
-    // LAUNCH!
-    ISEShell.CurrentDirectory = ISERunDir;
-
-    // Redirect STDERR to STDOUT
-    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
-    var ISEProcess = ISEShell.Exec( ISECmdLine );
-    
-    // BEGIN file creation
-    var wbemFlagReturnImmediately = 0x10;
-    var wbemFlagForwardOnly = 0x20;
-    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
-    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
-    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
-    var NOC = 0;
-    var NOLP = 0;
-    var TPM = 0;
-    var cpuInfos = new Enumerator(processor);
-    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
-        var cpuInfo = cpuInfos.item();
-        NOC += cpuInfo.NumberOfCores;
-        NOLP += cpuInfo.NumberOfLogicalProcessors;
-    }
-    var csInfos = new Enumerator(computerSystem);
-    for(;!csInfos.atEnd(); csInfos.moveNext()) {
-        var csInfo = csInfos.item();
-        TPM += csInfo.TotalPhysicalMemory;
-    }
-
-    var ISEHOSTCORE = NOLP
-    var ISEMEMTOTAL = TPM
-
-    var ISENetwork = WScript.CreateObject( "WScript.Network" );
-    var ISEHost = ISENetwork.ComputerName;
-    var ISEUser = ISENetwork.UserName;
-    var ISEPid = ISEProcess.ProcessID;
-    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
-    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
-    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
-    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
-			    "\" Owner=\"" + ISEUser + 
-			    "\" Host=\"" + ISEHost + 
-			    "\" Pid=\"" + ISEPid +
-			    "\" HostCore=\"" + ISEHOSTCORE +
-			    "\" HostMemory=\"" + ISEMEMTOTAL +
-			    "\">" );
-    ISEBeginFile.WriteLine( "    </Process>" );
-    ISEBeginFile.WriteLine( "</ProcessHandle>" );
-    ISEBeginFile.Close();
-    
-    var ISEOutStr = ISEProcess.StdOut;
-    var ISEErrStr = ISEProcess.StdErr;
-    
-    // WAIT for ISEStep to finish
-    while ( ISEProcess.Status == 0 ) {
-      
-      // dump stdout then stderr - feels a little arbitrary
-      while ( !ISEOutStr.AtEndOfStream ) {
-        ISEStdOut( ISEOutStr.ReadLine() );
-      }  
-      
-      WScript.Sleep( 100 );
-    }
-
-    ISEExitCode = ISEProcess.ExitCode;
-  }
-
-  ISELogFileStr.Close();
-
-  // END/ERROR file creation
-  if ( ISEExitCode != 0 ) {    
-    ISETouchFile( ISEStep, "error" );
-    
-  } else {
-    ISETouchFile( ISEStep, "end" );
-  }
-
-  return ISEExitCode;
-}
-
-
-//
-// UTILITIES
-//
-function ISEStdOut( ISELine ) {
-
-  ISELogFileStr.WriteLine( ISELine );
-  
-  if ( ISELogEcho ) {
-    WScript.StdOut.WriteLine( ISELine );
-  }
-}
-
-function ISEStdErr( ISELine ) {
-  
-  ISELogFileStr.WriteLine( ISELine );
-
-  if ( ISELogEcho ) {
-    WScript.StdErr.WriteLine( ISELine );
-  }
-}
-
-function ISETouchFile( ISERoot, ISEStatus ) {
-
-  var ISETFile = 
-    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
-  ISETFile.Close();
-}
-
-function ISEOpenFile( ISEFilename ) {
-
-  // This function has been updated to deal with a problem seen in CR #870871.
-  // In that case the user runs a script that runs impl_1, and then turns around
-  // and runs impl_1 -to_step write_bitstream. That second run takes place in
-  // the same directory, which means we may hit some of the same files, and in
-  // particular, we will open the runme.log file. Even though this script closes
-  // the file (now), we see cases where a subsequent attempt to open the file
-  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
-  // play? In any case, we try to work around this by first waiting if the file
-  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
-  // and try to open the file 10 times with a one second delay after each attempt.
-  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
-  // If there is an unrecognized exception when trying to open the file, we output
-  // an error message and write details to an exception.log file.
-  var ISEFullPath = ISERunDir + "/" + ISEFilename;
-  if (ISEFileSys.FileExists(ISEFullPath)) {
-    // File is already there. This could be a problem. Wait in case it is still in use.
-    WScript.Sleep(5000);
-  }
-  var i;
-  for (i = 0; i < 10; ++i) {
-    try {
-      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
-    } catch (exception) {
-      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
-      if (error_code == 52) { // 52 is bad file name or number.
-        // Wait a second and try again.
-        WScript.Sleep(1000);
-        continue;
-      } else {
-        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
-        var exceptionFilePath = ISERunDir + "/exception.log";
-        if (!ISEFileSys.FileExists(exceptionFilePath)) {
-          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
-          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
-          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
-          exceptionFile.WriteLine("\tException name: " + exception.name);
-          exceptionFile.WriteLine("\tException error code: " + error_code);
-          exceptionFile.WriteLine("\tException message: " + exception.message);
-          exceptionFile.Close();
-        }
-        throw exception;
-      }
-    }
-  }
-  // If we reached this point, we failed to open the file after 10 attempts.
-  // We need to error out.
-  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
-  WScript.Quit(1);
-}
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.sh
deleted file mode 100755
index e085d18..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/ISEWrap.sh
+++ /dev/null
@@ -1,85 +0,0 @@
-#!/bin/bash
-
-#
-#  Vivado(TM)
-#  ISEWrap.sh: Vivado Runs Script for UNIX
-#  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
-#  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
-#
-
-cmd_exists()
-{
-  command -v "$1" >/dev/null 2>&1
-}
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo ""                                        >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo ""                                        >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo ""                      >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo "    with args $@"      >> $HD_LOG
-echo ""                      >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-
-HostNameFile=/proc/sys/kernel/hostname
-if cmd_exists hostname
-then
-ISE_HOST=$(hostname)
-elif cmd_exists uname
-then
-ISE_HOST=$(uname -n)
-elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
-then
-ISE_HOST=$(cat $HostNameFile)
-elif [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST     #csh
-fi
-
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
-echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo "    </Process>"                                                                              >> $ISE_BEGINFILE
-echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
-    /bin/touch .$ISE_STEP.end.rst
-else
-    /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/clockInfo.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/clockInfo.txt
deleted file mode 100644
index ec4afe6..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/clockInfo.txt
+++ /dev/null
@@ -1,10 +0,0 @@
--------------------------------------
-| Tool Version : Vivado v.2026.1
-| Date         : Fri Sep 25 21:31:19 2026
-| Host         : IRON-B
-| Design       : design_1
-| Device       : xc7a35t-cpg236-1--
--------------------------------------
-
-For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/gen_run.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/gen_run.xml
deleted file mode 100644
index f17d199..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/gen_run.xml
+++ /dev/null
@@ -1,166 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1790371817">
-  <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
-  <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
-  <File Type="POSTROUTE-PHYSOPT-RQS" Name="soc_postroute_physopted.rqs"/>
-  <File Type="ROUTE-RQS" Name="soc_routed.rqs"/>
-  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
-  <File Type="RDI-RDI" Name="soc.vdi"/>
-  <File Type="BG-DRC" Name="soc.drc"/>
-  <File Type="BG-BGN" Name="soc.bgn"/>
-  <File Type="BITSTR-SYSDEF" Name="soc.sysdef"/>
-  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
-  <File Type="BITSTR-LTX" Name="soc.ltx"/>
-  <File Type="PL-LTX-FILE" Name="soc_pld.ltx"/>
-  <File Type="BOOT-LTX-FILE" Name="soc_boot.ltx"/>
-  <File Type="LTX-FILE" Name="soc.ltx"/>
-  <File Type="PL-BIF-FILE" Name="soc_pld.bif"/>
-  <File Type="BOOT-BIF-FILE" Name="soc_boot.bif"/>
-  <File Type="BIF-FILE" Name="soc.bif"/>
-  <File Type="MMI-FILE" Name="soc.mmi"/>
-  <File Type="RBD_FILE" Name="soc.rbd"/>
-  <File Type="NPI_FILE" Name="soc.npi"/>
-  <File Type="PL_UNMASK_RCDO_FILE" Name="soc_pld_unmask.rcdo"/>
-  <File Type="PL_UNMASK_MARKER_RCDO_FILE" Name="soc_pld_unmask_markers.rcdo"/>
-  <File Type="PL_MASK_RCDO_FILE" Name="soc_pld_mask.rcdo"/>
-  <File Type="PL_MARKER_RCDO_FILE" Name="soc_pld_markers.rcdo"/>
-  <File Type="PL-CLEAR-RCDO-FILE" Name="soc_pld_clear.rcdo"/>
-  <File Type="PL-RCDO-FILE" Name="soc_pld.rcdo"/>
-  <File Type="PL_UNMASK_RNPI_FILE" Name="soc_pld_unmask.rnpi"/>
-  <File Type="PL_SHUTDOWN_RNPI_FILE" Name="soc_pld_shutdown.rnpi"/>
-  <File Type="PL_MASK_RNPI_FILE" Name="soc_pld_mask.rnpi"/>
-  <File Type="PL_MARKER_RNPI_FILE" Name="soc_pld_markers.rnpi"/>
-  <File Type="PL_RNPI_FILE" Name="soc_pld.rnpi"/>
-  <File Type="BOOT_MARKER_RNPI_FILE" Name="soc_boot_markers.rnpi"/>
-  <File Type="BOOT_RNPI_FILE" Name="soc_boot.rnpi"/>
-  <File Type="MARKER-RCDO-FILE" Name="soc_markers.rcdo"/>
-  <File Type="MARKER-RNPI-FILE" Name="soc_markers.rnpi"/>
-  <File Type="RCDO-FILE" Name="soc.rcdo"/>
-  <File Type="RNPI_FILE" Name="soc.rnpi"/>
-  <File Type="CFI_FILE" Name="soc.cfi"/>
-  <File Type="RCFI_FILE" Name="soc.rcfi"/>
-  <File Type="PL-PDI-FILE" Name="soc_pld.pdi"/>
-  <File Type="BOOT-PDI-FILE" Name="soc_boot.pdi"/>
-  <File Type="PDI-FILE" Name="soc.pdi"/>
-  <File Type="BITSTR-MMI" Name="soc.mmi"/>
-  <File Type="BITSTR-BMM" Name="soc_bd.bmm"/>
-  <File Type="BITSTR-NKY" Name="soc.nky"/>
-  <File Type="BITSTR-RBT" Name="soc.rbt"/>
-  <File Type="BITSTR-MSK" Name="soc.msk"/>
-  <File Type="BG-BIN" Name="soc.bin"/>
-  <File Type="BG-WRITE-BITSTREAM-XML" Name="write_bitstream.xml"/>
-  <File Type="BG-XML" Name="soc.xml"/>
-  <File Type="BG-BIT" Name="soc.bit"/>
-  <File Type="NOC_SOLUTION_FILE" Name="soc.ncr"/>
-  <File Type="NOC_TRAFFIC_SPEC_FILE" Name="soc.nts"/>
-  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="soc_bus_skew_postroute_physopted.rpx"/>
-  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="soc_bus_skew_postroute_physopted.pb"/>
-  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="soc_bus_skew_postroute_physopted.rpt"/>
-  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="soc_timing_summary_postroute_physopted.rpx"/>
-  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="soc_timing_summary_postroute_physopted.pb"/>
-  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="soc_timing_summary_postroute_physopted.rpt"/>
-  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="soc_postroute_physopt_bb.dcp"/>
-  <File Type="POSTROUTE-PHYSOPT-DCP" Name="soc_postroute_physopt.dcp"/>
-  <File Type="ROUTE-RQS-PB" Name="soc_rqs_routed.pb"/>
-  <File Type="ROUTE-BUS-SKEW-RPX" Name="soc_bus_skew_routed.rpx"/>
-  <File Type="ROUTE-BUS-SKEW-PB" Name="soc_bus_skew_routed.pb"/>
-  <File Type="ROUTE-BUS-SKEW" Name="soc_bus_skew_routed.rpt"/>
-  <File Type="ROUTE-CLK" Name="soc_clock_utilization_routed.rpt"/>
-  <File Type="ROUTE-SIMILARITY" Name="soc_incremental_reuse_routed.rpt"/>
-  <File Type="ROUTE-TIMING-RPX" Name="soc_timing_summary_routed.rpx"/>
-  <File Type="ROUTE-TIMING-PB" Name="soc_timing_summary_routed.pb"/>
-  <File Type="ROUTE-TIMINGSUMMARY" Name="soc_timing_summary_routed.rpt"/>
-  <File Type="ROUTE-STATUS-PB" Name="soc_route_status.pb"/>
-  <File Type="ROUTE-STATUS" Name="soc_route_status.rpt"/>
-  <File Type="ROUTE-PWR-RPX" Name="soc_power_routed.rpx"/>
-  <File Type="ROUTE-PWR-SUM" Name="soc_power_summary_routed.pb"/>
-  <File Type="ROUTE-PWR" Name="soc_power_routed.rpt"/>
-  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="soc_methodology_drc_routed.pb"/>
-  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="soc_methodology_drc_routed.rpx"/>
-  <File Type="ROUTE-METHODOLOGY-DRC" Name="soc_methodology_drc_routed.rpt"/>
-  <File Type="ROUTE-DRC-RPX" Name="soc_drc_routed.rpx"/>
-  <File Type="ROUTE-DRC-PB" Name="soc_drc_routed.pb"/>
-  <File Type="ROUTE-DRC" Name="soc_drc_routed.rpt"/>
-  <File Type="ROUTE-UTIL-PB" Name="soc_utilization_routed.pb"/>
-  <File Type="ROUTE-UTIL" Name="soc_utilization_routed.rpt"/>
-  <File Type="ROUTE-BLACKBOX-DCP" Name="soc_routed_bb.dcp"/>
-  <File Type="ROUTE-DCP" Name="soc_routed.dcp"/>
-  <File Type="ROUTE-ERROR-DCP" Name="soc_routed_error.dcp"/>
-  <File Type="PHYSOPT-TIMING" Name="soc_timing_summary_physopted.rpt"/>
-  <File Type="PHYSOPT-DRC" Name="soc_drc_physopted.rpt"/>
-  <File Type="PHYSOPT-DCP" Name="soc_physopt.dcp"/>
-  <File Type="POSTPLACE-PWROPT-TIMING" Name="soc_timing_summary_postplace_pwropted.rpt"/>
-  <File Type="POSTPLACE-PWROPT-DCP" Name="soc_postplace_pwropt.dcp"/>
-  <File Type="PLACE-RQA-PB" Name="soc_rqa_placed.pb"/>
-  <File Type="PLACE-TIMING" Name="soc_timing_summary_placed.rpt"/>
-  <File Type="PLACE-PRE-SIMILARITY" Name="soc_incremental_reuse_pre_placed.rpt"/>
-  <File Type="PLACE-SIMILARITY" Name="soc_incremental_reuse_placed.rpt"/>
-  <File Type="PLACE-CTRL" Name="soc_control_sets_placed.rpt"/>
-  <File Type="PLACE-UTIL-PB" Name="soc_utilization_placed.pb"/>
-  <File Type="PLACE-UTIL" Name="soc_utilization_placed.rpt"/>
-  <File Type="PLACE-CLK" Name="soc_clock_utilization_placed.rpt"/>
-  <File Type="PLACE-IO" Name="soc_io_placed.rpt"/>
-  <File Type="PLACE-DCP" Name="soc_placed.dcp"/>
-  <File Type="PWROPT-TIMING" Name="soc_timing_summary_pwropted.rpt"/>
-  <File Type="PWROPT-DRC" Name="soc_drc_pwropted.rpt"/>
-  <File Type="PWROPT-DCP" Name="soc_pwropt.dcp"/>
-  <File Type="OPT-RQA-PB" Name="soc_rqa_opted.pb"/>
-  <File Type="OPT-TIMING" Name="soc_timing_summary_opted.rpt"/>
-  <File Type="OPT-HWDEF" Name="soc.hwdef"/>
-  <File Type="OPT-METHODOLOGY-DRC" Name="soc_methodology_drc_opted.rpt"/>
-  <File Type="OPT-UTIL-PB" Name="soc_utilization_opted.pb"/>
-  <File Type="OPT-UTIL" Name="soc_utilization_opted.rpt"/>
-  <File Type="OPT-DRC" Name="soc_drc_opted.rpt"/>
-  <File Type="OPT-DCP" Name="soc_opt.dcp"/>
-  <File Type="INIT-TIMING" Name="soc_timing_summary_init.rpt"/>
-  <File Type="REPORTS-TCL" Name="soc_reports.tcl"/>
-  <File Type="PA-TCL" Name="soc.tcl"/>
-  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
-    <Filter Type="Srcs"/>
-    <File Path="$PPRDIR/../../../../rtl/soc.sv">
-      <FileInfo>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
-        <Attr Name="UsedIn" Val="simulation"/>
-      </FileInfo>
-    </File>
-    <Config>
-      <Option Name="DesignMode" Val="RTL"/>
-      <Option Name="TopModule" Val="soc"/>
-      <Option Name="TopAutoSet" Val="TRUE"/>
-    </Config>
-  </FileSet>
-  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
-    <Filter Type="Constrs"/>
-    <File Path="$PSRCDIR/constrs_1/new/constraints.xdc">
-      <FileInfo>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
-      </FileInfo>
-    </File>
-    <Config>
-      <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/constraints.xdc"/>
-      <Option Name="ConstrsType" Val="XDC"/>
-    </Config>
-  </FileSet>
-  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
-    <Filter Type="Utils"/>
-    <Config>
-      <Option Name="TopAutoSet" Val="TRUE"/>
-    </Config>
-  </FileSet>
-  <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2026">
-      <Desc>Default settings for Implementation.</Desc>
-    </StratHandle>
-    <Step Id="init_design"/>
-    <Step Id="opt_design"/>
-    <Step Id="power_opt_design"/>
-    <Step Id="place_design"/>
-    <Step Id="post_place_power_opt_design"/>
-    <Step Id="phys_opt_design"/>
-    <Step Id="route_design"/>
-    <Step Id="post_route_phys_opt_design"/>
-    <Step Id="write_bitstream"/>
-  </Strategy>
-</GenRun>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/htr.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/htr.txt
deleted file mode 100644
index e90a97e..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/htr.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-#          the basic steps of a run.  Note that runme.bat/sh needs
-#          to be invoked for Vivado to track run status.
-# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-#
-
-vivado -log soc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/init_design.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/init_design.pb
deleted file mode 100644
index 651085b..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/init_design.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/opt_design.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/opt_design.pb
deleted file mode 100644
index 3908623..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/opt_design.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/phys_opt_design.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/phys_opt_design.pb
deleted file mode 100644
index 30a83a5..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/phys_opt_design.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/place_design.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/place_design.pb
deleted file mode 100644
index 206d65c..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/place_design.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/project.wdf b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/project.wdf
deleted file mode 100644
index 47781af..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/project.wdf
+++ /dev/null
@@ -1,31 +0,0 @@
-version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
-5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3432666436666137393436313435336538613235633164353863643335343333:506172656e742050412070726f6a656374204944:00
-eof:2107803377
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/route_design.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/route_design.pb
deleted file mode 100644
index f7b5ae3..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/route_design.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/rundef.js b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/rundef.js
deleted file mode 100644
index babd87f..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/rundef.js
+++ /dev/null
@@ -1,45 +0,0 @@
-//
-// Vivado(TM)
-// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-//
-
-echo "This script was generated under a different operating system."
-echo "Please update the PATH variable below, before executing this script"
-exit
-
-var WshShell = new ActiveXObject( "WScript.Shell" );
-var ProcEnv = WshShell.Environment( "Process" );
-var PathVal = ProcEnv("PATH");
-if ( PathVal.length == 0 ) {
-  PathVal = "/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64;/home/imar/vivado/2026.1/Vivado/bin;";
-} else {
-  PathVal = "/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64;/home/imar/vivado/2026.1/Vivado/bin;" + PathVal;
-}
-
-ProcEnv("PATH") = PathVal;
-
-var RDScrFP = WScript.ScriptFullName;
-var RDScrN = WScript.ScriptName;
-var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
-var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
-eval( EAInclude(ISEJScriptLib) );
-
-
-// pre-commands:
-ISETouchFile( "init_design", "begin" );
-ISEStep( "vivado",
-         "-log soc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace" );
-
-
-
-
-
-function EAInclude( EAInclFilename ) {
-  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
-  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
-  var EAIFContents = EAInclFile.ReadAll();
-  EAInclFile.Close();
-  return EAIFContents;
-}
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.bat b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.bat
deleted file mode 100644
index 829dfd8..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.bat
+++ /dev/null
@@ -1,12 +0,0 @@
-@echo off
-
-rem  Vivado (TM)
-rem  runme.bat: a Vivado-generated Script
-rem  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-rem  Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-set HD_SDIR=%~dp0
-cd /d "%HD_SDIR%"
-set PATH=%SYSTEMROOT%\system32;%PATH%
-cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.log b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.log
deleted file mode 100644
index f853b3d..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.log
+++ /dev/null
@@ -1,674 +0,0 @@
-
-*** Running vivado
-    with args -log soc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
-
-INFO: [Common 17-3922] A valid Vivado Design Suite BASIC license has been detected. Your current license is active and will expire on 25-sep-2027.
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:31:01 2026
-# Process ID         : 287718
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1
-# Command line       : vivado -log soc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 4069.591 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3633 MB
-#-----------------------------------------------------------
-
-****** Vivado v2026.1 (64-bit)
-  **** SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-  **** IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-  **** SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-  **** Start of session at: Fri Sep 25 21:31:01 2026
-    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-    ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-source soc.tcl -notrace
-Command: link_design -top soc -part xc7a35tcpg236-1
-Design is defaulting to srcset: sources_1
-Design is defaulting to constrset: constrs_1
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1888.398 ; gain = 0.000 ; free physical = 923 ; free virtual = 2877
-INFO: [Project 1-479] Netlist was created with Vivado 2026.1
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-Finished Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2084.984 ; gain = 0.000 ; free physical = 850 ; free virtual = 2767
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-link_design completed successfully
-Command: opt_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2100.859 ; gain = 11.871 ; free physical = 895 ; free virtual = 2750
-
-Starting Cache Timing Information Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2543.070 ; gain = 442.211 ; free physical = 719 ; free virtual = 2308
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 361 ; free virtual = 1887
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 362 ; free virtual = 1887
-Phase 1 Initialization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 362 ; free virtual = 1887
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1886
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-Phase 2 Timer Update And Timing Data Collection | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-Retarget | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Constant propagation | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Phase 5 Sweep | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Sweep | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-BUFG optimization | Checksum: 2ccbfae1c
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Shift Register Optimization | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Post Processing Netlist | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Phase 9 Finalization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
--------------------------------------------------------------------------------------------------------------------------
-|  Retarget                     |               0  |               0  |                                              0  |
-|  Constant propagation         |               0  |               0  |                                              0  |
-|  Sweep                        |               0  |               0  |                                              0  |
-|  BUFG optimization            |               0  |               0  |                                              0  |
-|  Shift Register Optimization  |               0  |               0  |                                              0  |
-|  Post Processing Netlist      |               0  |               0  |                                              0  |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-
-Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3025.000 ; gain = 936.012 ; free physical = 373 ; free virtual = 1891
-INFO: [Vivado 12-24828] Executing command : report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx
-Command: report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/imar/vivado/2026.1/data/ip'.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpt.
-report_drc completed successfully
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 343 ; free virtual = 1892
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 343 ; free virtual = 1892
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Write Physdb Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_opt.dcp' has been generated.
-Command: place_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 253805a09
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dcaf9957
-
-Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 328 ; free virtual = 1893
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 323 ; free virtual = 1892
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 323 ; free virtual = 1892
-Phase 1 Placer Initialization | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 276bf89f7
-
-Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 317 ; free virtual = 1888
-
-Phase 2.5 Global Place Phase2
-WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped.
-Phase 2.5 Global Place Phase2 | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-Phase 2 Global Placement | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23a6b1f2c
-
-Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 2d88372cf
-
-Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 2d88372cf
-
-Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 3 Detail Placement | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-Phase 4.1 Post Commit Optimization | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion 
- ____________________________________________________
-|           | Global Congestion | Short Congestion  |
-| Direction | Region Size       | Region Size       |
-|___________|___________________|___________________|
-|      North|                1x1|                1x1|
-|___________|___________________|___________________|
-|      South|                1x1|                1x1|
-|___________|___________________|___________________|
-|       East|                1x1|                1x1|
-|___________|___________________|___________________|
-|       West|                1x1|                1x1|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 4.3 Placer Reporting | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 316 ; free virtual = 1887
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Ending Placer Task | Checksum: 217bdf51d
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
-Running report generation with 2 threads.
-INFO: [Vivado 12-24828] Executing command : report_io -file soc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 293 ; free virtual = 1877
-INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file soc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 292 ; free virtual = 1876
-INFO: [Vivado 12-24828] Executing command : report_utilization -file soc_utilization_placed.rpt -pb soc_utilization_placed.pb
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_placed.dcp' has been generated.
-Command: phys_opt_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-50 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1869
-Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1869
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_physopt.dcp' has been generated.
-Command: route_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: af2004ed ConstDB: 0 ShapeSum: c81c93d9 RouteDB: a0815c57
-Post Restoration Checksum: NetGraph: 3ffc8d6a | NumContArr: 374debcd | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 211 ; free virtual = 1867
-
-Phase 2 Router Initialization
-INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
- Number of Nodes with overlaps = 0
-
-Router Utilization Summary
-  Global Vertical Routing Utilization    = 0 %
-  Global Horizontal Routing Utilization  = 0 %
-  Routable Net Status*
-  *Does not include unroutable nets such as driverless and loadless.
-  Run report_route_status for detailed report.
-  Number of Failed Nets               = 2
-    (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 2
-  Number of Partially Routed Nets     = 0
-  Number of Node Overlaps             = 0
-
-Phase 2 Router Initialization | Checksum: 30c8d576c
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 30c8d576c
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
- Number of Nodes with overlaps = 0
-Phase 4.1 Initial Net Routing Pass | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 4 Initial Routing | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
-Phase 5.1 Global Iteration 0 | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 5 Rip-up And Reroute | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 6 Delay and Skew Optimization
-Phase 6 Delay and Skew Optimization | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 7 Post Hold Fix
-
-Phase 7.1 Hold Fix Iter
-Phase 7.1 Hold Fix Iter | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 7 Post Hold Fix | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 8 Route finalize
-
-Router Utilization Summary
-  Global Vertical Routing Utilization    = 7.97257e-05 %
-  Global Horizontal Routing Utilization  = 0.000520562 %
-  Routable Net Status*
-  *Does not include unroutable nets such as driverless and loadless.
-  Run report_route_status for detailed report.
-  Number of Failed Nets               = 0
-    (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 0
-  Number of Partially Routed Nets     = 0
-  Number of Node Overlaps             = 0
-
-
---GLOBAL Congestion:
-Utilization threshold used for congestion level computation: 0.85
-Congestion Report
-North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
-South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions.
-East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
-West Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions.
-
-------------------------------
-Reporting congestion hotspots
-------------------------------
-Direction: North
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: South
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: East
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: West
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-
-Phase 8 Route finalize | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 9 Verifying routed nets
-
- Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-Total Elapsed time in route_design: 13.79 secs
-
-Phase 12 Post-Route Event Processing
-Phase 12 Post-Route Event Processing | Checksum: 1f8d8ab79
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: 1f8d8ab79
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Routing Is Done.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-route_design completed successfully
-route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-INFO: [Vivado 12-24828] Executing command : report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx
-Command: report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpt.
-report_drc completed successfully
-INFO: [Vivado 12-24828] Executing command : report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx
-Command: report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [DRC 23-133] Running Methodology with 8 threads
-INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpt.
-report_methodology completed successfully
-INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file soc_timing_summary_routed.rpt -pb soc_timing_summary_routed.pb -rpx soc_timing_summary_routed.rpx -warn_on_violation 
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
-WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
-INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
-Running report generation with 2 threads.
-INFO: [Vivado 12-24828] Executing command : report_route_status -file soc_route_status.rpt -pb soc_route_status.pb
-INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file soc_incremental_reuse_routed.rpt
-INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
-INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file soc_bus_skew_routed.rpt -pb soc_bus_skew_routed.pb -rpx soc_bus_skew_routed.rpx
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
-INFO: [Vivado 12-24828] Executing command : report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx
-Command: report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx
-WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
-Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-77 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
-report_power completed successfully
-INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file soc_clock_utilization_routed.rpt
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1874
-Write Physdb Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1874
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_routed.dcp' has been generated.
-Command: write_bitstream -force soc.bit
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-Running DRC as a precondition to command write_bitstream
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-Integrating Hard IP ELF/MEM with the PDI.
-INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
-Initializing bitstream generation complete. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 182 ; free virtual = 1868
-Loading data files...
-Loading site data...
-Loading route data...
-Processing options...
-Creating bitmap...
-Creating bitstream...
-Writing bitstream ./soc.bit...
-Generate Bitstream complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3148.266 ; gain = 58.246 ; free physical = 209 ; free virtual = 1748
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-88 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:34 . Memory (MB): peak = 3180.309 ; gain = 90.289 ; free physical = 173 ; free virtual = 1760
-INFO: [Common 17-206] Exiting Vivado at Fri Sep 25 21:32:09 2026...
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.sh
deleted file mode 100755
index 2091e55..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/runme.sh
+++ /dev/null
@@ -1,44 +0,0 @@
-#!/bin/bash
-
-# 
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-# 
-
-if [ -z "$PATH" ]; then
-  PATH=/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64:/home/imar/vivado/2026.1/Vivado/bin
-else
-  PATH=/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64:/home/imar/vivado/2026.1/Vivado/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
-  LD_LIBRARY_PATH=
-else
-  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
-     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
-     if [ $? -ne 0 ]
-     then
-         exit
-     fi
-}
-
-# pre-commands:
-/bin/touch .init_design.begin.rst
-EAStep vivado -log soc.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.bit b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.bit
deleted file mode 100644
index e61215e..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.bit
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.tcl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.tcl
deleted file mode 100644
index 049a574..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.tcl
+++ /dev/null
@@ -1,313 +0,0 @@
-namespace eval ::optrace {
-  variable script "/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.tcl"
-  variable category "vivado_impl"
-}
-
-# Try to connect to running dispatch if we haven't done so already.
-# This code assumes that the Tcl interpreter is not using threads,
-# since the ::dispatch::connected variable isn't mutex protected.
-if {![info exists ::dispatch::connected]} {
-  namespace eval ::dispatch {
-    variable connected false
-    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
-      set result "true"
-      if {[catch {
-        if {[lsearch -exact [package names] DispatchTcl] < 0} {
-          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
-        }
-        if {$result eq "false"} {
-          puts "WARNING: Could not load dispatch client library"
-        }
-        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
-        if { $connect_id eq "" } {
-          puts "WARNING: Could not initialize dispatch client"
-        } else {
-          puts "INFO: Dispatch client connection id - $connect_id"
-          set connected true
-        }
-      } catch_res]} {
-        puts "WARNING: failed to connect to dispatch server - $catch_res"
-      }
-    }
-  }
-}
-if {$::dispatch::connected} {
-  # Remove the dummy proc if it exists.
-  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
-    rename ::OPTRACE ""
-  }
-  proc ::OPTRACE { task action {tags {} } } {
-    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
-  }
-  # dispatch is generic. We specifically want to attach logging.
-  ::vitis_log::connect_client
-} else {
-  # Add dummy proc if it doesn't exist.
-  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
-    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
-        # Do nothing
-    }
-  }
-}
-
-proc start_step { step } {
-  set stopFile ".stop.rst"
-  if {[file isfile .stop.rst]} {
-    puts ""
-    puts "*** Halting run - EA reset detected ***"
-    puts ""
-    puts ""
-    return -code error
-  }
-  set beginFile ".$step.begin.rst"
-  set platform "$::tcl_platform(platform)"
-  set user "$::tcl_platform(user)"
-  set pid [pid]
-  set host ""
-  if { [string equal $platform unix] } {
-    if { [info exist ::env(HOSTNAME)] } {
-      set host $::env(HOSTNAME)
-    } elseif { [info exist ::env(HOST)] } {
-      set host $::env(HOST)
-    }
-  } else {
-    if { [info exist ::env(COMPUTERNAME)] } {
-      set host $::env(COMPUTERNAME)
-    }
-  }
-  set ch [open $beginFile w]
-  puts $ch "<?xml version=\"1.0\"?>"
-  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
-  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
-  puts $ch "    </Process>"
-  puts $ch "</ProcessHandle>"
-  close $ch
-}
-
-proc end_step { step } {
-  set endFile ".$step.end.rst"
-  set ch [open $endFile w]
-  close $ch
-}
-
-proc step_failed { step } {
-  set endFile ".$step.error.rst"
-  set ch [open $endFile w]
-  close $ch
-OPTRACE "impl_1" END { }
-}
-
-
-OPTRACE "impl_1" START { ROLLUP_1 }
-OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
-start_step init_design
-set ACTIVE_STEP init_design
-set rc [catch {
-  create_msg_db init_design.pb
-  set_param chipscope.maxJobs 1
-  set_param xicom.use_bs_reader 1
-  set_param general.usePosixSpawnForFork 1
-  set_param runs.launchOptions { -jobs 4  }
-OPTRACE "create in-memory project" START { }
-  create_project -in_memory -part xc7a35tcpg236-1
-  set_property design_mode GateLvl [current_fileset]
-  set_param project.singleFileAddWarning.threshold 0
-OPTRACE "create in-memory project" END { }
-OPTRACE "set parameters" START { }
-  set_property webtalk.parent_dir /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt [current_project]
-  set_property parent.project_path /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr [current_project]
-  set_property ip_output_repo /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip [current_project]
-  set_property ip_cache_permissions {read write} [current_project]
-OPTRACE "set parameters" END { }
-OPTRACE "add files" START { }
-  add_files -quiet /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp
-OPTRACE "read constraints: implementation" START { }
-  read_xdc /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc
-OPTRACE "read constraints: implementation" END { }
-OPTRACE "read constraints: implementation_pre" START { }
-OPTRACE "read constraints: implementation_pre" END { }
-OPTRACE "add files" END { }
-OPTRACE "link_design" START { }
-  link_design -top soc -part xc7a35tcpg236-1 
-OPTRACE "link_design" END { }
-OPTRACE "gray box cells" START { }
-OPTRACE "gray box cells" END { }
-OPTRACE "init_design_reports" START { REPORT }
-OPTRACE "init_design_reports" END { }
-OPTRACE "init_design_write_hwdef" START { }
-OPTRACE "init_design_write_hwdef" END { }
-  close_msg_db -file init_design.pb
-} RESULT]
-if {$rc} {
-  step_failed init_design
-  return -code error $RESULT
-} else {
-  end_step init_design
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "Phase: Init Design" END { }
-OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
-start_step opt_design
-set ACTIVE_STEP opt_design
-set rc [catch {
-  create_msg_db opt_design.pb
-OPTRACE "read constraints: opt_design" START { }
-OPTRACE "read constraints: opt_design" END { }
-OPTRACE "opt_design" START { }
-  opt_design 
-OPTRACE "opt_design" END { }
-OPTRACE "read constraints: opt_design_post" START { }
-OPTRACE "read constraints: opt_design_post" END { }
-OPTRACE "opt_design reports" START { REPORT }
-  set_param project.isImplRun true
-  generate_parallel_reports -reports { "report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx"  }
-  set_param project.isImplRun false
-OPTRACE "opt_design reports" END { }
-OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
-  write_checkpoint -force soc_opt.dcp
-OPTRACE "Opt Design: write_checkpoint" END { }
-  close_msg_db -file opt_design.pb
-} RESULT]
-if {$rc} {
-  step_failed opt_design
-  return -code error $RESULT
-} else {
-  end_step opt_design
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "Phase: Opt Design" END { }
-OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
-start_step place_design
-set ACTIVE_STEP place_design
-set rc [catch {
-  create_msg_db place_design.pb
-OPTRACE "read constraints: place_design" START { }
-OPTRACE "read constraints: place_design" END { }
-  if { [llength [get_debug_cores -quiet] ] > 0 }  { 
-OPTRACE "implement_debug_core" START { }
-    implement_debug_core 
-OPTRACE "implement_debug_core" END { }
-  } 
-OPTRACE "place_design" START { }
-  set_param project.isImplRun true
-  place_design 
-  set_param project.isImplRun false
-OPTRACE "place_design" END { }
-OPTRACE "read constraints: place_design_post" START { }
-OPTRACE "read constraints: place_design_post" END { }
-OPTRACE "place_design reports" START { REPORT }
-  set_param project.isImplRun true
-  generate_parallel_reports -reports { "report_io -file soc_io_placed.rpt" "report_utilization -file soc_utilization_placed.rpt -pb soc_utilization_placed.pb" "report_control_sets -verbose -file soc_control_sets_placed.rpt"  }
-  set_param project.isImplRun false
-OPTRACE "place_design reports" END { }
-OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
-  write_checkpoint -force soc_placed.dcp
-OPTRACE "Place Design: write_checkpoint" END { }
-  close_msg_db -file place_design.pb
-} RESULT]
-if {$rc} {
-  step_failed place_design
-  return -code error $RESULT
-} else {
-  end_step place_design
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "Phase: Place Design" END { }
-OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
-start_step phys_opt_design
-set ACTIVE_STEP phys_opt_design
-set rc [catch {
-  create_msg_db phys_opt_design.pb
-OPTRACE "read constraints: phys_opt_design" START { }
-OPTRACE "read constraints: phys_opt_design" END { }
-OPTRACE "phys_opt_design" START { }
-  phys_opt_design 
-OPTRACE "phys_opt_design" END { }
-OPTRACE "read constraints: phys_opt_design_post" START { }
-OPTRACE "read constraints: phys_opt_design_post" END { }
-OPTRACE "phys_opt_design report" START { REPORT }
-OPTRACE "phys_opt_design report" END { }
-OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
-  write_checkpoint -force soc_physopt.dcp
-OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
-  close_msg_db -file phys_opt_design.pb
-} RESULT]
-if {$rc} {
-  step_failed phys_opt_design
-  return -code error $RESULT
-} else {
-  end_step phys_opt_design
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "Phase: Physical Opt Design" END { }
-OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
-start_step route_design
-set ACTIVE_STEP route_design
-set rc [catch {
-  create_msg_db route_design.pb
-OPTRACE "read constraints: route_design" START { }
-OPTRACE "read constraints: route_design" END { }
-OPTRACE "route_design" START { }
-  route_design 
-OPTRACE "route_design" END { }
-OPTRACE "read constraints: route_design_post" START { }
-OPTRACE "read constraints: route_design_post" END { }
-OPTRACE "route_design reports" START { REPORT }
-  set_param project.isImplRun true
-  generate_parallel_reports -reports { "report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx" "report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx" "report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx" "report_route_status -file soc_route_status.rpt -pb soc_route_status.pb" "report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file soc_timing_summary_routed.rpt -pb soc_timing_summary_routed.pb -rpx soc_timing_summary_routed.rpx -warn_on_violation " "report_incremental_reuse -file soc_incremental_reuse_routed.rpt" "report_clock_utilization -file soc_clock_utilization_routed.rpt" "report_bus_skew -warn_on_violation -file soc_bus_skew_routed.rpt -pb soc_bus_skew_routed.pb -rpx soc_bus_skew_routed.rpx"  }
-  set_param project.isImplRun false
-OPTRACE "route_design reports" END { }
-OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
-  write_checkpoint -force soc_routed.dcp
-OPTRACE "Route Design: write_checkpoint" END { }
-OPTRACE "route_design misc" START { }
-  close_msg_db -file route_design.pb
-} RESULT]
-if {$rc} {
-OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
-OPTRACE "route_design write_checkpoint" END { }
-  write_checkpoint -force soc_routed_error.dcp
-  step_failed route_design
-  return -code error $RESULT
-} else {
-  end_step route_design
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "route_design misc" END { }
-OPTRACE "Phase: Route Design" END { }
-OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
-OPTRACE "write_bitstream setup" START { }
-start_step write_bitstream
-set ACTIVE_STEP write_bitstream
-set rc [catch {
-  create_msg_db write_bitstream.pb
-OPTRACE "read constraints: write_bitstream" START { }
-OPTRACE "read constraints: write_bitstream" END { }
-  catch { write_mem_info -force -no_partial_mmi soc.mmi }
-OPTRACE "write_bitstream setup" END { }
-OPTRACE "write_bitstream" START { }
-  write_bitstream -force soc.bit 
-OPTRACE "write_bitstream" END { }
-OPTRACE "write_bitstream misc" START { }
-OPTRACE "read constraints: write_bitstream_post" START { }
-OPTRACE "read constraints: write_bitstream_post" END { }
-  catch {write_debug_probes -quiet -force soc}
-  catch {file copy -force soc.ltx debug_nets.ltx}
-  close_msg_db -file write_bitstream.pb
-} RESULT]
-if {$rc} {
-  step_failed write_bitstream
-  return -code error $RESULT
-} else {
-  end_step write_bitstream
-  unset ACTIVE_STEP 
-}
-
-OPTRACE "write_bitstream misc" END { }
-OPTRACE "Phase: Write Bitstream" END { }
-OPTRACE "impl_1" END { }
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi
deleted file mode 100644
index d031eed..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi
+++ /dev/null
@@ -1,661 +0,0 @@
-INFO: [Common 17-3922] A valid Vivado Design Suite BASIC license has been detected. Your current license is active and will expire on 25-sep-2027.
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:31:01 2026
-# Process ID         : 287718
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1
-# Command line       : vivado -log soc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 4069.591 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3633 MB
-#-----------------------------------------------------------
-source soc.tcl -notrace
-Command: link_design -top soc -part xc7a35tcpg236-1
-Design is defaulting to srcset: sources_1
-Design is defaulting to constrset: constrs_1
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1888.398 ; gain = 0.000 ; free physical = 923 ; free virtual = 2877
-INFO: [Project 1-479] Netlist was created with Vivado 2026.1
-INFO: [Project 1-570] Preparing netlist for logic optimization
-Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-Finished Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2084.984 ; gain = 0.000 ; free physical = 850 ; free virtual = 2767
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-link_design completed successfully
-Command: opt_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-Running DRC as a precondition to command opt_design
-
-Starting DRC Task
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Project 1-461] DRC finished with 0 Errors
-INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-
-Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2100.859 ; gain = 11.871 ; free physical = 895 ; free virtual = 2750
-
-Starting Cache Timing Information Task
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2543.070 ; gain = 442.211 ; free physical = 719 ; free virtual = 2308
-
-Starting Logic Optimization Task
-
-Phase 1 Initialization
-
-Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 361 ; free virtual = 1887
-
-Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 362 ; free virtual = 1887
-Phase 1 Initialization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 362 ; free virtual = 1887
-
-Phase 2 Timer Update And Timing Data Collection
-
-Phase 2.1 Detect if minReqCache needed
-Phase 2.1 Detect if minReqCache needed | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1886
-
-Phase 2.2 Timer Update
-Phase 2.2 Timer Update | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-
-Phase 2.3 Timing Data Collection
-Phase 2.3 Timing Data Collection | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-Phase 2 Timer Update And Timing Data Collection | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-
-Phase 3 Retarget
-INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
-INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1887
-Retarget | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
-
-Phase 4 Constant propagation
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Constant propagation | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
-
-Phase 5 Sweep
-INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Phase 5 Sweep | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2960.984 ; gain = 0.000 ; free physical = 365 ; free virtual = 1889
-Sweep | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
-
-Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-BUFG optimization | Checksum: 2ccbfae1c
-INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
-
-Phase 7 Shift Register Optimization
-INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Shift Register Optimization | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
-
-Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Post Processing Netlist | Checksum: 2ccbfae1c
-INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
-
-Phase 9 Finalization
-
-Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-
-Phase 9.2 Verifying Netlist Connectivity
-
-Starting Connectivity Check Task
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Phase 9 Finalization | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-Opt_design Change Summary
-=========================
-
-
--------------------------------------------------------------------------------------------------------------------------
-|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
--------------------------------------------------------------------------------------------------------------------------
-|  Retarget                     |               0  |               0  |                                              0  |
-|  Constant propagation         |               0  |               0  |                                              0  |
-|  Sweep                        |               0  |               0  |                                              0  |
-|  BUFG optimization            |               0  |               0  |                                              0  |
-|  Shift Register Optimization  |               0  |               0  |                                              0  |
-|  Post Processing Netlist      |               0  |               0  |                                              0  |
--------------------------------------------------------------------------------------------------------------------------
-
-
-Ending Logic Optimization Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3025.000 ; gain = 64.016 ; free physical = 377 ; free virtual = 1891
-
-Starting Power Optimization Task
-INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-
-Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 2ccbfae1c
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 377 ; free virtual = 1891
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-opt_design completed successfully
-opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3025.000 ; gain = 936.012 ; free physical = 373 ; free virtual = 1891
-INFO: [Vivado 12-24828] Executing command : report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx
-Command: report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx
-INFO: [IP_Flow 19-234] Refreshing IP repositories
-INFO: [IP_Flow 19-1704] No user IP repositories specified
-INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/imar/vivado/2026.1/data/ip'.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpt.
-report_drc completed successfully
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 343 ; free virtual = 1892
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 343 ; free virtual = 1892
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-Write Physdb Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 342 ; free virtual = 1893
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_opt.dcp' has been generated.
-Command: place_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-Running DRC as a precondition to command place_design
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
-INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
-INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
-
-Starting Placer Task
-
-Phase 1 Placer Initialization
-
-Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 253805a09
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 334 ; free virtual = 1892
-
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dcaf9957
-
-Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 328 ; free virtual = 1893
-
-Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 323 ; free virtual = 1892
-
-Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.31 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 323 ; free virtual = 1892
-Phase 1 Placer Initialization | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2 Global Placement
-
-Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 2cc18cde5
-
-Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3025.000 ; gain = 0.000 ; free physical = 321 ; free virtual = 1892
-
-Phase 2.4 Global Place Phase1
-Phase 2.4 Global Place Phase1 | Checksum: 276bf89f7
-
-Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.27 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 317 ; free virtual = 1888
-
-Phase 2.5 Global Place Phase2
-WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped.
-Phase 2.5 Global Place Phase2 | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-Phase 2 Global Placement | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3 Detail Placement
-
-Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 2c9fc53a7
-
-Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.31 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23a6b1f2c
-
-Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 2d88372cf
-
-Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 2d88372cf
-
-Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.32 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1888
-
-Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.81 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 3 Detail Placement | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.83 ; elapsed = 00:00:00.39 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4 Post Placement Optimization and Clean-Up
-
-Phase 4.1 Post Commit Optimization
-Phase 4.1 Post Commit Optimization | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.3 Placer Reporting
-
-Phase 4.3.1 Print Estimated Congestion
-INFO: [Place 30-612] Post-Placement Estimated Congestion 
- ____________________________________________________
-|           | Global Congestion | Short Congestion  |
-| Direction | Region Size       | Region Size       |
-|___________|___________________|___________________|
-|      North|                1x1|                1x1|
-|___________|___________________|___________________|
-|      South|                1x1|                1x1|
-|___________|___________________|___________________|
-|       East|                1x1|                1x1|
-|___________|___________________|___________________|
-|       West|                1x1|                1x1|
-|___________|___________________|___________________|
-
-Phase 4.3.1 Print Estimated Congestion | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 4.3 Placer Reporting | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.89 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-
-Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 316 ; free virtual = 1887
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2f2a6bbbd
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-Ending Placer Task | Checksum: 217bdf51d
-
-Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.41 . Memory (MB): peak = 3057.008 ; gain = 32.008 ; free physical = 316 ; free virtual = 1887
-41 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-place_design completed successfully
-INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel.
-Running report generation with 2 threads.
-INFO: [Vivado 12-24828] Executing command : report_io -file soc_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 293 ; free virtual = 1877
-INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file soc_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3057.008 ; gain = 0.000 ; free physical = 292 ; free virtual = 1876
-INFO: [Vivado 12-24828] Executing command : report_utilization -file soc_utilization_placed.rpt -pb soc_utilization_placed.pb
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 284 ; free virtual = 1871
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_placed.dcp' has been generated.
-Command: phys_opt_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-
-Starting Initial Update Timing Task
-
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-50 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-phys_opt_design completed successfully
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1870
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1869
-Write Physdb Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 278 ; free virtual = 1869
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_physopt.dcp' has been generated.
-Command: route_design
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-
-
-Starting Routing Task
-INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
-
-Phase 1 Build RT Design
-Checksum: PlaceDB: af2004ed ConstDB: 0 ShapeSum: c81c93d9 RouteDB: a0815c57
-Post Restoration Checksum: NetGraph: 3ffc8d6a | NumContArr: 374debcd | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 211 ; free virtual = 1867
-
-Phase 2 Router Initialization
-INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
-
-Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 1fc9c6e71
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
- Number of Nodes with overlaps = 0
-
-Router Utilization Summary
-  Global Vertical Routing Utilization    = 0 %
-  Global Horizontal Routing Utilization  = 0 %
-  Routable Net Status*
-  *Does not include unroutable nets such as driverless and loadless.
-  Run report_route_status for detailed report.
-  Number of Failed Nets               = 2
-    (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 2
-  Number of Partially Routed Nets     = 0
-  Number of Node Overlaps             = 0
-
-Phase 2 Router Initialization | Checksum: 30c8d576c
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 3 Global Routing
-Phase 3 Global Routing | Checksum: 30c8d576c
-
-Time (s): cpu = 00:00:15 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 4 Initial Routing
-
-Phase 4.1 Initial Net Routing Pass
- Number of Nodes with overlaps = 0
-Phase 4.1 Initial Net Routing Pass | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 4 Initial Routing | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 5 Rip-up And Reroute
-
-Phase 5.1 Global Iteration 0
-Phase 5.1 Global Iteration 0 | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 5 Rip-up And Reroute | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 6 Delay and Skew Optimization
-Phase 6 Delay and Skew Optimization | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 7 Post Hold Fix
-
-Phase 7.1 Hold Fix Iter
-Phase 7.1 Hold Fix Iter | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-Phase 7 Post Hold Fix | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 8 Route finalize
-
-Router Utilization Summary
-  Global Vertical Routing Utilization    = 7.97257e-05 %
-  Global Horizontal Routing Utilization  = 0.000520562 %
-  Routable Net Status*
-  *Does not include unroutable nets such as driverless and loadless.
-  Run report_route_status for detailed report.
-  Number of Failed Nets               = 0
-    (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 0
-  Number of Partially Routed Nets     = 0
-  Number of Node Overlaps             = 0
-
-
---GLOBAL Congestion:
-Utilization threshold used for congestion level computation: 0.85
-Congestion Report
-North Dir 1x1 Area, Max Cong = 0%, No Congested Regions.
-South Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions.
-East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
-West Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions.
-
-------------------------------
-Reporting congestion hotspots
-------------------------------
-Direction: North
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: South
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: East
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-Direction: West
-----------------
-Congested clusters found at Level 0
-Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
-
-Phase 8 Route finalize | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1867
-
-Phase 9 Verifying routed nets
-
- Verification completed successfully
-Phase 9 Verifying routed nets | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Phase 10 Depositing Routes
-Phase 10 Depositing Routes | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Phase 11 Post Process Routing
-Phase 11 Post Process Routing | Checksum: 2aa248a37
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-Total Elapsed time in route_design: 13.79 secs
-
-Phase 12 Post-Route Event Processing
-Phase 12 Post-Route Event Processing | Checksum: 1f8d8ab79
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-INFO: [Route 35-16] Router Completed Successfully
-Ending Routing Task | Checksum: 1f8d8ab79
-
-Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-
-Routing Is Done.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-57 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
-route_design completed successfully
-route_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:14 . Memory (MB): peak = 3074.016 ; gain = 0.000 ; free physical = 210 ; free virtual = 1866
-INFO: [Vivado 12-24828] Executing command : report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx
-Command: report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpt.
-report_drc completed successfully
-INFO: [Vivado 12-24828] Executing command : report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx
-Command: report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [DRC 23-133] Running Methodology with 8 threads
-INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpt.
-report_methodology completed successfully
-INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file soc_timing_summary_routed.rpt -pb soc_timing_summary_routed.pb -rpx soc_timing_summary_routed.rpx -warn_on_violation 
-INFO: [Timing 38-35] Done setting XDC timing constraints.
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
-WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
-INFO: [Vivado 12-24838] Running report commands "report_bus_skew, report_incremental_reuse, report_route_status" in parallel.
-Running report generation with 2 threads.
-INFO: [Vivado 12-24828] Executing command : report_route_status -file soc_route_status.rpt -pb soc_route_status.pb
-INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file soc_incremental_reuse_routed.rpt
-INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
-INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file soc_bus_skew_routed.rpt -pb soc_bus_skew_routed.pb -rpx soc_bus_skew_routed.rpx
-INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
-INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
-INFO: [Vivado 12-24828] Executing command : report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx
-Command: report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx
-WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected.
-Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
-Running Vector-less Activity Propagation...
-
-Finished Running Vector-less Activity Propagation
-77 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
-report_power completed successfully
-INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file soc_clock_utilization_routed.rpt
-INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Writing XDEF routing.
-Writing XDEF routing logical nets.
-Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1875
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1874
-Write Physdb Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 205 ; free virtual = 1874
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_routed.dcp' has been generated.
-Command: write_bitstream -force soc.bit
-Attempting to get a license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Implementation' and/or device 'xc7a35t'
-Running DRC as a precondition to command write_bitstream
-INFO: [IP_Flow 19-1839] IP Catalog is up to date.
-INFO: [DRC 23-27] Running DRC with 8 threads
-INFO: [Vivado 12-3199] DRC finished with 0 Errors
-INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
-Integrating Hard IP ELF/MEM with the PDI.
-INFO: [Designutils 20-2272] Running write_bitstream with 4 threads.
-Initializing bitstream generation complete. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 3090.020 ; gain = 0.000 ; free physical = 182 ; free virtual = 1868
-Loading data files...
-Loading site data...
-Loading route data...
-Processing options...
-Creating bitmap...
-Creating bitstream...
-Writing bitstream ./soc.bit...
-Generate Bitstream complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 3148.266 ; gain = 58.246 ; free physical = 209 ; free virtual = 1748
-INFO: [Vivado 12-1842] Bitgen Completed Successfully.
-INFO: [Common 17-83] Releasing license: Vivado_Implementation
-88 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
-write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:34 . Memory (MB): peak = 3180.309 ; gain = 90.289 ; free physical = 173 ; free virtual = 1760
-INFO: [Common 17-206] Exiting Vivado at Fri Sep 25 21:32:09 2026...
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.pb
deleted file mode 100644
index 3390588..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpt
deleted file mode 100644
index 568b864..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpt
+++ /dev/null
@@ -1,16 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:34 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_bus_skew -warn_on_violation -file soc_bus_skew_routed.rpt -pb soc_bus_skew_routed.pb -rpx soc_bus_skew_routed.rpx
-| Design       : soc
-| Device       : 7a35t-cpg236
-| Speed File   : -1  PRODUCTION 1.23 2018-06-13
-| Design State : Routed
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Bus Skew Report
-
-No bus skew constraints
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpx
deleted file mode 100644
index 6f48431..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_bus_skew_routed.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_clock_utilization_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_clock_utilization_routed.rpt
deleted file mode 100644
index 9fb4cb2..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_clock_utilization_routed.rpt
+++ /dev/null
@@ -1,146 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:35 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_clock_utilization -file soc_clock_utilization_routed.rpt
-| Design       : soc
-| Device       : 7a35t-cpg236
-| Speed File   : -1  PRODUCTION 1.23 2018-06-13
-| Design State : Routed
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Clock Utilization Report
-
-Table of Contents
------------------
-1. Clock Primitive Utilization
-2. Global Clock Resources
-3. Global Clock Source Details
-4. Clock Regions: Key Resource Utilization
-5. Clock Regions : Global Clock Summary
-6. Device Cell Placement Summary for Global Clock g0
-7. Clock Region Cell Placement per Global Clock: Region X0Y2
-
-1. Clock Primitive Utilization
-------------------------------
-
-+----------+------+-----------+-----+--------------+--------+
-| Type     | Used | Available | LOC | Clock Region | Pblock |
-+----------+------+-----------+-----+--------------+--------+
-| BUFGCTRL |    1 |        32 |   0 |            0 |      0 |
-| BUFH     |    0 |        72 |   0 |            0 |      0 |
-| BUFIO    |    0 |        20 |   0 |            0 |      0 |
-| BUFMR    |    0 |        10 |   0 |            0 |      0 |
-| BUFR     |    0 |        20 |   0 |            0 |      0 |
-| MMCM     |    0 |         5 |   0 |            0 |      0 |
-| PLL      |    0 |         5 |   0 |            0 |      0 |
-+----------+------+-----------+-----+--------------+--------+
-
-
-2. Global Clock Resources
--------------------------
-
-+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+---------------------------+--------------------+
-| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin                | Net                |
-+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+---------------------------+--------------------+
-| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 1 |           1 |               0 |              |       | refclk_i_IBUF_BUFG_inst/O | refclk_i_IBUF_BUFG |
-+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+---------------------------+--------------------+
-* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
-** Non-Clock Loads column represents cell count of non-clock pin loads
-
-
-3. Global Clock Source Details
-------------------------------
-
-+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+----------------------+---------------+
-| Source Id | Global Id | Driver Type/Pin | Constraint | Site      | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin           | Net           |
-+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+----------------------+---------------+
-| src0      | g0        | IBUF/O          | IOB_X1Y26  | IOB_X1Y26 | X1Y0         |           1 |               0 |                     |              | refclk_i_IBUF_inst/O | refclk_i_IBUF |
-+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+----------------------+---------------+
-* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
-** Non-Clock Loads column represents cell count of non-clock pin loads
-
-
-4. Clock Regions: Key Resource Utilization
-------------------------------------------
-
-+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
-|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-| X0Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1200 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
-| X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1200 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  1500 |    0 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
-| X0Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    1 |  1800 |    0 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y2              |    0 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |   950 |    0 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
-+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-* Global Clock column represents track count; while other columns represents cell counts
-
-
-5. Clock Regions : Global Clock Summary
----------------------------------------
-
-All Modules
-+----+----+----+
-|    | X0 | X1 |
-+----+----+----+
-| Y2 |  0 |  0 |
-| Y1 |  0 |  0 |
-| Y0 |  0 |  0 |
-+----+----+----+
-
-
-6. Device Cell Placement Summary for Global Clock g0
-----------------------------------------------------
-
-+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------------+
-| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                |
-+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------------+
-| g0        | BUFG/O          | n/a               |       |             |               |           1 |        0 |              0 |        0 | refclk_i_IBUF_BUFG |
-+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+--------------------+
-* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
-** IO Loads column represents load cell count of IO types
-*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
-**** GT Loads column represents load cell count of GT types
-
-
-+----+----+----+-----------------------+
-|    | X0 | X1 | HORIZONTAL PROG DELAY |
-+----+----+----+-----------------------+
-| Y2 |  1 |  0 |                     0 |
-| Y1 |  0 |  0 |                     - |
-| Y0 |  0 |  0 |                     - |
-+----+----+----+-----------------------+
-
-
-7. Clock Region Cell Placement per Global Clock: Region X0Y2
-------------------------------------------------------------
-
-+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------+
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------+
-| g0        | n/a   | BUFG/O          | None       |           1 |               0 |  1 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | refclk_i_IBUF_BUFG |
-+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------+
-* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
-** Non-Clock Loads column represents cell count of non-clock pin loads
-*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
-
-
-
-# Location of BUFG Primitives 
-set_property LOC BUFGCTRL_X0Y0 [get_cells refclk_i_IBUF_BUFG_inst]
-
-# Location of IO Primitives which is load of clock spine
-
-# Location of clock ports
-set_property LOC IOB_X1Y26 [get_ports refclk_i]
-
-# Clock net "refclk_i_IBUF_BUFG" driven by instance "refclk_i_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0"
-#startgroup
-create_pblock {CLKAG_refclk_i_IBUF_BUFG}
-add_cells_to_pblock [get_pblocks  {CLKAG_refclk_i_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="refclk_i_IBUF_BUFG"}]]]
-resize_pblock [get_pblocks {CLKAG_refclk_i_IBUF_BUFG}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}
-#endgroup
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_control_sets_placed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_control_sets_placed.rpt
deleted file mode 100644
index 2796e1b..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_control_sets_placed.rpt
+++ /dev/null
@@ -1,79 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:20 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_control_sets -verbose -file soc_control_sets_placed.rpt
-| Design       : soc
-| Device       : xc7a35t
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Control Set Information
-
-Table of Contents
------------------
-1. Summary
-2. Histogram
-3. Flip-Flop Distribution
-4. Detailed Control Set Information
-
-1. Summary
-----------
-
-+----------------------------------------------------------+-------+
-|                          Status                          | Count |
-+----------------------------------------------------------+-------+
-| Total control sets                                       |     1 |
-|    Minimum number of control sets                        |     1 |
-|    Addition due to synthesis replication                 |     0 |
-|    Addition due to physical synthesis replication        |     0 |
-| Unused register locations in slices containing registers |     7 |
-+----------------------------------------------------------+-------+
-* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
-** Run report_qor_suggestions for automated merging and remapping suggestions
-
-
-2. Histogram
-------------
-
-+--------------------+-------+
-|       Fanout       | Count |
-+--------------------+-------+
-| Total control sets |     1 |
-| >= 0 to < 4        |     1 |
-| >= 4 to < 6        |     0 |
-| >= 6 to < 8        |     0 |
-| >= 8 to < 10       |     0 |
-| >= 10 to < 12      |     0 |
-| >= 12 to < 14      |     0 |
-| >= 14 to < 16      |     0 |
-| >= 16              |     0 |
-+--------------------+-------+
-* Control sets can be remapped at either synth_design or opt_design
-
-
-3. Flip-Flop Distribution
--------------------------
-
-+--------------+-----------------------+------------------------+-----------------+--------------+
-| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
-+--------------+-----------------------+------------------------+-----------------+--------------+
-| No           | No                    | No                     |               1 |            1 |
-| No           | No                    | Yes                    |               0 |            0 |
-| No           | Yes                   | No                     |               0 |            0 |
-| Yes          | No                    | No                     |               0 |            0 |
-| Yes          | No                    | Yes                    |               0 |            0 |
-| Yes          | Yes                   | No                     |               0 |            0 |
-+--------------+-----------------------+------------------------+-----------------+--------------+
-
-
-4. Detailed Control Set Information
------------------------------------
-
-+---------------------+---------------+------------------+------------------+----------------+--------------+
-|     Clock Signal    | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
-+---------------------+---------------+------------------+------------------+----------------+--------------+
-|  refclk_i_IBUF_BUFG |               |                  |                1 |              1 |         1.00 |
-+---------------------+---------------+------------------+------------------+----------------+--------------+
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.pb
deleted file mode 100644
index 70698d1..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpt
deleted file mode 100644
index 2b42eec..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpt
+++ /dev/null
@@ -1,49 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:19 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_drc -file soc_drc_opted.rpt -pb soc_drc_opted.pb -rpx soc_drc_opted.rpx
-| Design       : soc
-| Device       : xc7a35tcpg236-1
-| Speed File   : -1
-| Design State : Synthesized
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Report DRC
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
-            Netlist: netlist
-          Floorplan: design_1
-      Design limits: <entire design considered>
-           Ruledeck: default
-             Max checks: <unlimited>
-             Checks found: 1
-+----------+----------+-----------------------------------------------------+--------+
-| Rule     | Severity | Description                                         | Checks |
-+----------+----------+-----------------------------------------------------+--------+
-| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
-+----------+----------+-----------------------------------------------------+--------+
-
-2. REPORT DETAILS
------------------
-CFGBVS-1#1 Warning
-Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
-Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
-
- set_property CFGBVS value1 [current_design]
- #where value1 is either VCCO or GND
-
- set_property CONFIG_VOLTAGE value2 [current_design]
- #where value2 is the voltage provided to configuration bank 0
-
-Refer to the device configuration user guide for more information.
-Related violations: <none>
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpx
deleted file mode 100644
index 6020013..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_opted.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.pb
deleted file mode 100644
index 70698d1..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpt
deleted file mode 100644
index fd298ab..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpt
+++ /dev/null
@@ -1,49 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:34 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_drc -file soc_drc_routed.rpt -pb soc_drc_routed.pb -rpx soc_drc_routed.rpx
-| Design       : soc
-| Device       : xc7a35tcpg236-1
-| Speed File   : -1
-| Design State : Fully Routed
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Report DRC
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
-            Netlist: netlist
-          Floorplan: design_1
-      Design limits: <entire design considered>
-           Ruledeck: default
-             Max checks: <unlimited>
-             Checks found: 1
-+----------+----------+-----------------------------------------------------+--------+
-| Rule     | Severity | Description                                         | Checks |
-+----------+----------+-----------------------------------------------------+--------+
-| CFGBVS-1 | Warning  | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1      |
-+----------+----------+-----------------------------------------------------+--------+
-
-2. REPORT DETAILS
------------------
-CFGBVS-1#1 Warning
-Missing CFGBVS and CONFIG_VOLTAGE Design Properties  
-Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
-
- set_property CFGBVS value1 [current_design]
- #where value1 is either VCCO or GND
-
- set_property CONFIG_VOLTAGE value2 [current_design]
- #where value2 is the voltage provided to configuration bank 0
-
-Refer to the device configuration user guide for more information.
-Related violations: <none>
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpx
deleted file mode 100644
index 2f2a39d..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_drc_routed.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_io_placed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_io_placed.rpt
deleted file mode 100644
index 5e4fc54..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_io_placed.rpt
+++ /dev/null
@@ -1,280 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version              : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date                      : Fri Sep 25 21:31:19 2026
-| Host                      : IRON-B running 64-bit unknown
-| Command                   : report_io -file soc_io_placed.rpt
-| Design                    : soc
-| Device                    : xc7a35t
-| Speed File                : -1
-| Package                   : cpg236
-| Package Version           : FINAL 2014-02-19
-| Package Pin Delay Version : VERS. 2.0 2014-02-19
-----------------------------------------------------------------------------------------------------------------------------------------------------------
-
-IO Information
-
-Table of Contents
------------------
-1. Summary
-2. IO Assignments by Package Pin
-
-1. Summary
-----------
-
-+---------------+
-| Total User IO |
-+---------------+
-|             3 |
-+---------------+
-
-
-2. IO Assignments by Package Pin
---------------------------------
-
-+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
-| Pin Number | Signal Name | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
-+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
-| A1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| A2         |             |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| A4         |             |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| A6         |             |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| A8         |             |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| A10        |             |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A11        |             | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A12        |             | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A13        |             | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A14        | pwr_good_o  | High Range | IO_L6P_T0_16                 | OUTPUT        | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
-| A15        | reset_ni    | High Range | IO_L6N_T0_VREF_16            | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      | PULLUP    |          |      | NONE             |              |                   |              |
-| A16        |             | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A17        |             | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A18        |             | High Range | IO_L19N_T3_VREF_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| A19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B1         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B2         |             |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B4         |             |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B6         |             |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B8         |             |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B10        |             |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B11        |             | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B12        |             | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B13        |             | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B14        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| B15        |             | High Range | IO_L11N_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B16        |             | High Range | IO_L13N_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B17        |             | High Range | IO_L14N_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B18        |             | High Range | IO_L19P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| B19        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| C1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| C3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| C4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| C5         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| C7         |             |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C8         |             | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C9         |             | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| C11        |             | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C12        |             | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C13        |             | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C14        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| C15        |             | High Range | IO_L11P_T1_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C16        |             | High Range | IO_L13P_T2_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C17        |             | High Range | IO_L14P_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| C18        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| C19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| D1         |             |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| D2         |             |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| D3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| D17        |             | High Range | IO_0_14                      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| D18        |             | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| D19        |             | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| E1         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| E2         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| E3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| E17        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| E18        |             | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| E19        |             | High Range | IO_L3N_T0_DQS_EMCCLK_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| F1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| F2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| F3         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| F17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| F18        |             | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| F19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| G1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| G2         |             | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G3         |             | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G7         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| G9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| G12        |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| G13        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| G17        |             | High Range | IO_L5N_T0_D07_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G18        |             | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| G19        |             | High Range | IO_L4N_T0_D05_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H1         |             | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H2         |             | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H3         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| H7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| H8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| H9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| H12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| H13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
-| H17        |             | High Range | IO_L5P_T0_D06_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| H18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| H19        |             | High Range | IO_L4P_T0_D04_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J1         |             | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J2         |             | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J3         |             | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| J8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| J9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| J10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| J12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| J13        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
-| J17        |             | High Range | IO_L7P_T1_D09_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J18        |             | High Range | IO_L7N_T1_D10_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| J19        |             | High Range | IO_L6N_T0_D08_VREF_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| K1         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| K2         |             | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| K3         |             | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| K7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| K8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| K12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| K13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| K17        |             | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| K18        |             | High Range | IO_L8N_T1_D12_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| K19        |             | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L1         |             | High Range | IO_L6N_T0_VREF_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L2         |             | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L3         |             | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| L8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| L9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| L10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| L12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| L13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| L17        |             | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L18        |             | High Range | IO_L8P_T1_D11_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| L19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| M1         |             | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M2         |             | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M3         |             | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M7         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| M8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| M9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| M10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M12        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| M13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| M17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| M18        |             | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| M19        |             | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N1         |             | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N2         |             | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N3         |             | High Range | IO_L12P_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N7         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| N8         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| N9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| N10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| N13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| N17        |             | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N18        |             | High Range | IO_L9P_T1_DQS_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| N19        |             | High Range | IO_L9N_T1_DQS_D13_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| P1         |             | High Range | IO_L19N_T3_VREF_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| P2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| P3         |             | High Range | IO_L12N_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| P17        |             | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| P18        |             | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| P19        |             | High Range | IO_L10P_T1_D14_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| R1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| R2         |             | High Range | IO_L1P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| R3         |             | High Range | IO_L2P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| R17        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| R18        |             | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| R19        |             | High Range | IO_L10N_T1_D15_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T1         |             | High Range | IO_L3P_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T2         |             | High Range | IO_L1N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T3         |             | High Range | IO_L2N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T17        |             | High Range | IO_L17P_T2_A14_D30_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T18        |             | High Range | IO_L17N_T2_A13_D29_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| T19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| U1         |             | High Range | IO_L3N_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U2         |             | High Range | IO_L9N_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U3         |             | High Range | IO_L9P_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U4         |             | High Range | IO_L11P_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U5         |             | High Range | IO_L16P_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| U7         |             | High Range | IO_L19P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U8         |             | High Range | IO_L14P_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| U10        |             | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U11        |             | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U12        |             | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U13        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| U14        |             | High Range | IO_25_14                     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U15        |             | High Range | IO_L23P_T3_A03_D19_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U16        |             | High Range | IO_L23N_T3_A02_D18_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U17        |             | High Range | IO_L18P_T2_A12_D28_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U18        |             | High Range | IO_L18N_T2_A11_D27_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| U19        |             | High Range | IO_L15P_T2_DQS_RDWR_B_14     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V1         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| V2         |             | High Range | IO_L5P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V3         |             | High Range | IO_L6P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V4         |             | High Range | IO_L11N_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V5         |             | High Range | IO_L16N_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V6         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
-| V7         |             | High Range | IO_L19N_T3_VREF_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V8         |             | High Range | IO_L14N_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V9         |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
-| V10        |             | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V11        |             | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V12        |             | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V13        |             | High Range | IO_L24P_T3_A01_D17_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V14        |             | High Range | IO_L24N_T3_A00_D16_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V15        |             | High Range | IO_L21P_T3_DQS_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V16        |             | High Range | IO_L19P_T3_A10_D26_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V17        |             | High Range | IO_L19N_T3_A09_D25_VREF_14   | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| V18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| V19        |             | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| W2         |             | High Range | IO_L5N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W3         |             | High Range | IO_L6N_T0_VREF_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W4         |             | High Range | IO_L12N_T1_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W5         | refclk_i    | High Range | IO_L12P_T1_MRCC_34           | INPUT         | LVCMOS33    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
-| W6         |             | High Range | IO_L13N_T2_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W7         |             | High Range | IO_L13P_T2_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W8         |             | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W9         |             | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W10        |             | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W11        |             | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
-| W13        |             | High Range | IO_L22P_T3_A05_D21_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W14        |             | High Range | IO_L22N_T3_A04_D20_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W15        |             | High Range | IO_L21N_T3_DQS_A06_D22_14    | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W16        |             | High Range | IO_L20P_T3_A08_D24_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W17        |             | High Range | IO_L20N_T3_A07_D23_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W18        |             | High Range | IO_L16P_T2_CSI_B_14          | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-| W19        |             | High Range | IO_L16N_T2_A15_D31_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
-+------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
-* Default value
-** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.pb
deleted file mode 100644
index 76bee50..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpt
deleted file mode 100644
index 38028fd..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpt
+++ /dev/null
@@ -1,40 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:34 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_methodology -file soc_methodology_drc_routed.rpt -pb soc_methodology_drc_routed.pb -rpx soc_methodology_drc_routed.rpx
-| Design       : soc
-| Device       : xc7a35tcpg236-1
-| Speed File   : -1
-| Design State : Fully Routed
------------------------------------------------------------------------------------------------------------------------------------------------
-
-Report Methodology
-
-Table of Contents
------------------
-1. REPORT SUMMARY
-2. REPORT DETAILS
-
-1. REPORT SUMMARY
------------------
-            Netlist: netlist
-          Floorplan: design_1
-      Design limits: <entire design considered>
-             Max checks: <unlimited>
-             Checks found: 1
-+-----------+------------------+-----------------------------+--------+
-| Rule      | Severity         | Description                 | Checks |
-+-----------+------------------+-----------------------------+--------+
-| TIMING-17 | Critical Warning | Non-clocked sequential cell | 1      |
-+-----------+------------------+-----------------------------+--------+
-
-2. REPORT DETAILS
------------------
-TIMING-17#1 Critical Warning
-Non-clocked sequential cell  
-The clock pin pwr_good_o_reg/C is not reached by a timing clock
-Related violations: <none>
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpx
deleted file mode 100644
index e1543fb..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_methodology_drc_routed.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_opt.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_opt.dcp
deleted file mode 100644
index 059e73f..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_opt.dcp
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_physopt.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_physopt.dcp
deleted file mode 100644
index e69eaea..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_physopt.dcp
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_placed.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_placed.dcp
deleted file mode 100644
index 099d9f4..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_placed.dcp
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpt
deleted file mode 100644
index fe12eba..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpt
+++ /dev/null
@@ -1,142 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version     : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date             : Fri Sep 25 21:31:35 2026
-| Host             : IRON-B running 64-bit unknown
-| Command          : report_power -file soc_power_routed.rpt -pb soc_power_summary_routed.pb -rpx soc_power_routed.rpx
-| Design           : soc
-| Device           : xc7a35tcpg236-1
-| Design State     : routed
-| Grade            : commercial
-| Process          : typical
-| Characterization : Production
--------------------------------------------------------------------------------------------------------------------------------------------------
-
-Power Report
-
-Table of Contents
------------------
-1. Summary
-1.1 On-Chip Components
-1.2 Power Supply Summary
-1.3 Confidence Level
-2. Settings
-2.1 Environment
-2.2 Clock Constraints
-3. Detailed Reports
-3.1 By Hierarchy
-
-1. Summary
-----------
-
-+--------------------------+--------------+
-| Total On-Chip Power (W)  | 0.827        |
-| Design Power Budget (W)  | Unspecified* |
-| Power Budget Margin (W)  | NA           |
-| Dynamic (W)              | 0.753        |
-| Device Static (W)        | 0.073        |
-| Effective TJA (C/W)      | 5.0          |
-| Max Ambient (C)          | 80.9         |
-| Junction Temperature (C) | 29.1         |
-| Confidence Level         | Low          |
-| Setting File             | ---          |
-| Simulation Activity File | ---          |
-| Design Nets Matched      | NA           |
-+--------------------------+--------------+
-* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
-
-
-1.1 On-Chip Components
-----------------------
-
-+--------------+-----------+----------+-----------+-----------------+
-| On-Chip      | Power (W) | Used     | Available | Utilization (%) |
-+--------------+-----------+----------+-----------+-----------------+
-| Slice Logic  |     0.006 |        4 |       --- |             --- |
-|   BUFG       |     0.006 |        1 |        32 |            3.13 |
-|   Register   |    <0.001 |        1 |     41600 |           <0.01 |
-|   Others     |     0.000 |        2 |       --- |             --- |
-| Signals      |     0.011 |        4 |       --- |             --- |
-| I/O          |     0.737 |        3 |       106 |            2.83 |
-| Static Power |     0.073 |          |           |                 |
-| Total        |     0.827 |          |           |                 |
-+--------------+-----------+----------+-----------+-----------------+
-
-
-1.2 Power Supply Summary
-------------------------
-
-+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
-+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint    |       1.000 |     0.036 |       0.025 |      0.011 |       NA    | Unspecified | NA         |
-| Vccaux    |       1.800 |     0.039 |       0.027 |      0.013 |       NA    | Unspecified | NA         |
-| Vcco33    |       3.300 |     0.207 |       0.206 |      0.001 |       NA    | Unspecified | NA         |
-| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
-| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
-+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-
-
-1.3 Confidence Level
---------------------
-
-+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
-| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
-+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
-| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
-| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
-| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
-| Internal nodes activity     | High       | User specified more than 25% of internal nodes         |                                                                                                                    |
-| Device models               | High       | Device models are Production                           |                                                                                                                    |
-|                             |            |                                                        |                                                                                                                    |
-| Overall confidence level    | Low        |                                                        |                                                                                                                    |
-+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
-
-
-2. Settings
------------
-
-2.1 Environment
----------------
-
-+-----------------------+--------------------------+
-| Ambient Temp (C)      | 25.0                     |
-| ThetaJA (C/W)         | 5.0                      |
-| Airflow (LFM)         | 250                      |
-| Heat Sink             | medium (Medium Profile)  |
-| ThetaSA (C/W)         | 4.6                      |
-| Board Selection       | medium (10"x10")         |
-| # of Board Layers     | 12to15 (12 to 15 Layers) |
-| Board Temperature (C) | 25.0                     |
-+-----------------------+--------------------------+
-
-
-2.2 Clock Constraints
----------------------
-
-+-------+--------+-----------------+
-| Clock | Domain | Constraint (ns) |
-+-------+--------+-----------------+
-
-
-3. Detailed Reports
--------------------
-
-3.1 By Hierarchy
-----------------
-
-+------+-----------+
-| Name | Power (W) |
-+------+-----------+
-| soc  |     0.753 |
-+------+-----------+
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpx
deleted file mode 100644
index 3ac9eea..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_routed.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_summary_routed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_summary_routed.pb
deleted file mode 100644
index 17b2f23..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_power_summary_routed.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.pb
deleted file mode 100644
index a79137f..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.rpt
deleted file mode 100644
index 4fadb96..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_route_status.rpt
+++ /dev/null
@@ -1,11 +0,0 @@
-Design Route Status
-                                               :      # nets :
-   ------------------------------------------- : ----------- :
-   # of logical nets.......................... :           9 :
-       # of nets not needing routing.......... :           5 :
-           # of internally routed nets........ :           5 :
-       # of routable nets..................... :           4 :
-           # of fully routed nets............. :           4 :
-       # of nets with routing errors.......... :           0 :
-   ------------------------------------------- : ----------- :
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_routed.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_routed.dcp
deleted file mode 100644
index 9274189..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_routed.dcp
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.pb
deleted file mode 100644
index 4526e93..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.pb
+++ /dev/null
@@ -1,2 +0,0 @@
-
-2012.4�)Timing analysis from Implemented netlist.
-\ No newline at end of file
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpt
deleted file mode 100644
index 2aea36e..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpt
+++ /dev/null
@@ -1,306 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:34 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_timing_summary -max_paths 10 -routable_nets -report_unconstrained -file soc_timing_summary_routed.rpt -pb soc_timing_summary_routed.pb -rpx soc_timing_summary_routed.rpx -warn_on_violation
-| Design       : soc
-| Device       : 7a35t-cpg236
-| Speed File   : -1  PRODUCTION 1.23 2018-06-13
-| Design State : Routed
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-
-Timing Summary Report
-
-------------------------------------------------------------------------------------------------
-| Timer Settings
-| --------------
-------------------------------------------------------------------------------------------------
-
-  Enable Multi Corner Analysis               :  Yes
-  Enable Pessimism Removal                   :  Yes
-  Pessimism Removal Resolution               :  Nearest Common Node
-  Enable Input Delay Default Clock           :  No
-  Enable Preset / Clear Arcs                 :  No
-  Disable Flight Delays                      :  No
-  Ignore I/O Paths                           :  No
-  Timing Early Launch at Borrowing Latches   :  No
-  Borrow Time for Max Delay Exceptions       :  Yes
-  Merge Timing Exceptions                    :  Yes
-  Inter-SLR Compensation                     :  Conservative
-
-  Corner  Analyze    Analyze    
-  Name    Max Paths  Min Paths  
-  ------  ---------  ---------  
-  Slow    Yes        Yes        
-  Fast    Yes        Yes        
-
-
-------------------------------------------------------------------------------------------------
-| Report Methodology
-| ------------------
-------------------------------------------------------------------------------------------------
-
-Rule       Severity          Description                  Violations  
----------  ----------------  ---------------------------  ----------  
-TIMING-17  Critical Warning  Non-clocked sequential cell  1           
-
-Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
-
-
-
-check_timing report
-
-Table of Contents
------------------
-1. checking no_clock (1)
-2. checking constant_clock (0)
-3. checking pulse_width_clock (0)
-4. checking unconstrained_internal_endpoints (1)
-5. checking no_input_delay (1)
-6. checking no_output_delay (1)
-7. checking multiple_clock (0)
-8. checking generated_clocks (0)
-9. checking loops (0)
-10. checking partial_input_delay (0)
-11. checking partial_output_delay (0)
-12. checking latch_loops (0)
-
-1. checking no_clock (1)
-------------------------
- There is 1 register/latch pin with no clock driven by root clock pin: refclk_i (HIGH)
-
-
-2. checking constant_clock (0)
-------------------------------
- There are 0 register/latch pins with constant_clock.
-
-
-3. checking pulse_width_clock (0)
----------------------------------
- There are 0 register/latch pins which need pulse_width check
-
-
-4. checking unconstrained_internal_endpoints (1)
-------------------------------------------------
- There is 1 pin that is not constrained for maximum delay. (HIGH)
-
- There are 0 pins that are not constrained for maximum delay due to constant clock.
-
-
-5. checking no_input_delay (1)
-------------------------------
- There is 1 input port with no input delay specified. (HIGH)
-
- There are 0 input ports with no input delay but user has a false path constraint.
-
-
-6. checking no_output_delay (1)
--------------------------------
- There is 1 port with no output delay specified. (HIGH)
-
- There are 0 ports with no output delay but user has a false path constraint
-
- There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
-
-
-7. checking multiple_clock (0)
-------------------------------
- There are 0 register/latch pins with multiple clocks.
-
-
-8. checking generated_clocks (0)
---------------------------------
- There are 0 generated clocks that are not connected to a clock source.
-
-
-9. checking loops (0)
----------------------
- There are 0 combinational loops in the design.
-
-
-10. checking partial_input_delay (0)
-------------------------------------
- There are 0 input ports with partial input delay specified.
-
-
-11. checking partial_output_delay (0)
--------------------------------------
- There are 0 ports with partial output delay specified.
-
-
-12. checking latch_loops (0)
-----------------------------
- There are 0 combinational latch loops in the design through latch input
-
-
-
-------------------------------------------------------------------------------------------------
-| Design Timing Summary
-| ---------------------
-------------------------------------------------------------------------------------------------
-
-    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
-        inf        0.000                      0                    2          inf        0.000                      0                    2           NA           NA                      NA                    NA  
-
-
-There are no user specified timing constraints.
-
-
-------------------------------------------------------------------------------------------------
-| Clock Summary
-| -------------
-------------------------------------------------------------------------------------------------
-
-
-------------------------------------------------------------------------------------------------
-| Intra Clock Table
-| -----------------
-------------------------------------------------------------------------------------------------
-
-Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
------             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
-
-
-------------------------------------------------------------------------------------------------
-| Inter Clock Table
-| -----------------
-------------------------------------------------------------------------------------------------
-
-From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
-----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
-
-
-------------------------------------------------------------------------------------------------
-| Other Path Groups Table
-| -----------------------
-------------------------------------------------------------------------------------------------
-
-Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
-----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
-
-
-------------------------------------------------------------------------------------------------
-| User Ignored Path Table
-| -----------------------
-------------------------------------------------------------------------------------------------
-
-Path Group    From Clock    To Clock    
-----------    ----------    --------    
-
-
-------------------------------------------------------------------------------------------------
-| Unconstrained Path Table
-| ------------------------
-------------------------------------------------------------------------------------------------
-
-Path Group    From Clock    To Clock    
-----------    ----------    --------    
-(none)                                    
-
-
-------------------------------------------------------------------------------------------------
-| Timing Details
-| --------------
-------------------------------------------------------------------------------------------------
-
-
---------------------------------------------------------------------------------------
-Path Group:  (none)
-From Clock:  
-  To Clock:  
-
-Max Delay             2 Endpoints
-Min Delay             2 Endpoints
---------------------------------------------------------------------------------------
-
-
-Max Delay Paths
---------------------------------------------------------------------------------------
-Slack:                    inf
-  Source:                 pwr_good_o_reg/C
-                            (rising edge-triggered cell FDRE)
-  Destination:            pwr_good_o
-                            (output port)
-  Path Group:             (none)
-  Path Type:              Max at Slow Process Corner
-  Data Path Delay:        5.648ns  (logic 3.976ns (70.396%)  route 1.672ns (29.604%))
-  Logic Levels:           2  (FDRE=1 OBUF=1)
-
-    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-  -------------------------------------------------------------------    -------------------
-    SLICE_X0Y137         FDRE                         0.000     0.000 r  pwr_good_o_reg/C
-    SLICE_X0Y137         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  pwr_good_o_reg/Q
-                         net (fo=1, routed)           1.672     2.128    pwr_good_o_OBUF
-    A14                  OBUF (Prop_obuf_I_O)         3.520     5.648 r  pwr_good_o_OBUF_inst/O
-                         net (fo=0)                   0.000     5.648    pwr_good_o
-    A14                                                               r  pwr_good_o
-  -------------------------------------------------------------------    -------------------
-
-Slack:                    inf
-  Source:                 reset_ni
-                            (input port)
-  Destination:            pwr_good_o_reg/D
-  Path Group:             (none)
-  Path Type:              Max at Slow Process Corner
-  Data Path Delay:        2.208ns  (logic 1.448ns (65.596%)  route 0.760ns (34.404%))
-  Logic Levels:           1  (IBUF=1)
-
-    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-  -------------------------------------------------------------------    -------------------
-    A15                                               0.000     0.000 r  reset_ni
-                         net (fo=0)                   0.000     0.000    reset_ni
-    A15                  IBUF (Prop_ibuf_I_O)         1.448     1.448 r  reset_ni_IBUF_inst/O
-                         net (fo=1, routed)           0.760     2.208    reset_ni_IBUF
-    SLICE_X0Y137         FDRE                                         r  pwr_good_o_reg/D
-  -------------------------------------------------------------------    -------------------
-
-
-
-
-
-Min Delay Paths
---------------------------------------------------------------------------------------
-Slack:                    inf
-  Source:                 reset_ni
-                            (input port)
-  Destination:            pwr_good_o_reg/D
-  Path Group:             (none)
-  Path Type:              Min at Fast Process Corner
-  Data Path Delay:        0.516ns  (logic 0.216ns (41.936%)  route 0.300ns (58.064%))
-  Logic Levels:           1  (IBUF=1)
-
-    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-  -------------------------------------------------------------------    -------------------
-    A15                                               0.000     0.000 r  reset_ni
-                         net (fo=0)                   0.000     0.000    reset_ni
-    A15                  IBUF (Prop_ibuf_I_O)         0.216     0.216 r  reset_ni_IBUF_inst/O
-                         net (fo=1, routed)           0.300     0.516    reset_ni_IBUF
-    SLICE_X0Y137         FDRE                                         r  pwr_good_o_reg/D
-  -------------------------------------------------------------------    -------------------
-
-Slack:                    inf
-  Source:                 pwr_good_o_reg/C
-                            (rising edge-triggered cell FDRE)
-  Destination:            pwr_good_o
-                            (output port)
-  Path Group:             (none)
-  Path Type:              Min at Fast Process Corner
-  Data Path Delay:        1.685ns  (logic 1.362ns (80.830%)  route 0.323ns (19.170%))
-  Logic Levels:           2  (FDRE=1 OBUF=1)
-
-    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-  -------------------------------------------------------------------    -------------------
-    SLICE_X0Y137         FDRE                         0.000     0.000 r  pwr_good_o_reg/C
-    SLICE_X0Y137         FDRE (Prop_fdre_C_Q)         0.141     0.141 r  pwr_good_o_reg/Q
-                         net (fo=1, routed)           0.323     0.464    pwr_good_o_OBUF
-    A14                  OBUF (Prop_obuf_I_O)         1.221     1.685 r  pwr_good_o_OBUF_inst/O
-                         net (fo=0)                   0.000     1.685    pwr_good_o
-    A14                                                               r  pwr_good_o
-  -------------------------------------------------------------------    -------------------
-
-
-
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpx b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpx
deleted file mode 100644
index 93f1b50..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_timing_summary_routed.rpx
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.pb
deleted file mode 100644
index fd6ee0b..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.rpt
deleted file mode 100644
index ff48897..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc_utilization_placed.rpt
+++ /dev/null
@@ -1,210 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:31:20 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_utilization -file soc_utilization_placed.rpt -pb soc_utilization_placed.pb
-| Design       : soc
-| Device       : xc7a35tcpg236-1
-| Speed File   : -1
-| Design State : Fully Placed
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Slice Logic Distribution
-3. Memory
-4. DSP
-5. IO and GT Specific
-6. Clocking
-7. Specific Feature
-8. Primitives
-9. Black Boxes
-10. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+------------+-----------+-------+
-|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
-+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs              |    0 |     0 |          0 |     20800 |  0.00 |
-|   LUT as Logic          |    0 |     0 |          0 |     20800 |  0.00 |
-|   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
-| Slice Registers         |    1 |     0 |          0 |     41600 | <0.01 |
-|   Register as Flip Flop |    1 |     0 |          0 |     41600 | <0.01 |
-|   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
-| F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
-| F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
-| Unique Control Sets     |    1 |       |          0 |      8150 |  0.01 |
-+-------------------------+------+-------+------------+-----------+-------+
-* Warning! LUT value is adjusted to account for LUT combining.
-** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0     |            _ |           - |            - |
-| 0     |            _ |           - |          Set |
-| 0     |            _ |           - |        Reset |
-| 0     |            _ |         Set |            - |
-| 0     |            _ |       Reset |            - |
-| 0     |          Yes |           - |            - |
-| 0     |          Yes |           - |          Set |
-| 0     |          Yes |           - |        Reset |
-| 0     |          Yes |         Set |            - |
-| 1     |          Yes |       Reset |            - |
-+-------+--------------+-------------+--------------+
-
-
-2. Slice Logic Distribution
----------------------------
-
-+--------------------------------------------+------+-------+------------+-----------+-------+
-|                  Site Type                 | Used | Fixed | Prohibited | Available | Util% |
-+--------------------------------------------+------+-------+------------+-----------+-------+
-| Slice                                      |    1 |     0 |          0 |      8150 |  0.01 |
-|   SLICEL                                   |    1 |     0 |            |           |       |
-|   SLICEM                                   |    0 |     0 |            |           |       |
-| LUT as Logic                               |    0 |     0 |          0 |     20800 |  0.00 |
-|   using O5 output only                     |    0 |       |            |           |       |
-|   using O6 output only                     |    0 |       |            |           |       |
-|   using O5 and O6                          |    0 |       |            |           |       |
-| LUT as Memory                              |    0 |     0 |          0 |      9600 |  0.00 |
-|   LUT as Distributed RAM                   |    0 |     0 |            |           |       |
-|     using O5 output only                   |    0 |       |            |           |       |
-|     using O6 output only                   |    0 |       |            |           |       |
-|     using O5 and O6                        |    0 |       |            |           |       |
-|   LUT as Shift Register                    |    0 |     0 |            |           |       |
-|     using O5 output only                   |    0 |       |            |           |       |
-|     using O6 output only                   |    0 |       |            |           |       |
-|     using O5 and O6                        |    0 |       |            |           |       |
-| Slice Registers                            |    1 |     0 |          0 |     41600 | <0.01 |
-|   Register driven from within the Slice    |    0 |       |            |           |       |
-|   Register driven from outside the Slice   |    1 |       |            |           |       |
-|     LUT in front of the register is unused |    1 |       |            |           |       |
-|     LUT in front of the register is used   |    0 |       |            |           |       |
-+--------------------------------------------+------+-------+------------+-----------+-------+
-
-
-3. Memory
----------
-
-+----------------+------+-------+------------+-----------+-------+
-|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
-+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile |    0 |     0 |          0 |        50 |  0.00 |
-|   RAMB36/FIFO* |    0 |     0 |          0 |        50 |  0.00 |
-|   RAMB18       |    0 |     0 |          0 |       100 |  0.00 |
-+----------------+------+-------+------------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-4. DSP
-------
-
-+-----------+------+-------+------------+-----------+-------+
-| Site Type | Used | Fixed | Prohibited | Available | Util% |
-+-----------+------+-------+------------+-----------+-------+
-| DSPs      |    0 |     0 |          0 |        90 |  0.00 |
-+-----------+------+-------+------------+-----------+-------+
-
-
-5. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+------------+-----------+-------+
-|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
-+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB                  |    3 |     3 |          0 |       106 |  2.83 |
-|   IOB Master Pads           |    2 |       |            |           |       |
-|   IOB Slave Pads            |    1 |       |            |           |       |
-| Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
-| Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
-| PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
-| PHASER_REF                  |    0 |     0 |          0 |         5 |  0.00 |
-| OUT_FIFO                    |    0 |     0 |          0 |        20 |  0.00 |
-| IN_FIFO                     |    0 |     0 |          0 |        20 |  0.00 |
-| IDELAYCTRL                  |    0 |     0 |          0 |         5 |  0.00 |
-| IBUFDS                      |    0 |     0 |          0 |       104 |  0.00 |
-| GTPE2_CHANNEL               |    0 |     0 |          0 |         2 |  0.00 |
-| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        20 |  0.00 |
-| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        20 |  0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       250 |  0.00 |
-| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
-| ILOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
-| OLOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
-+-----------------------------+------+-------+------------+-----------+-------+
-
-
-6. Clocking
------------
-
-+------------+------+-------+------------+-----------+-------+
-|  Site Type | Used | Fixed | Prohibited | Available | Util% |
-+------------+------+-------+------------+-----------+-------+
-| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
-| BUFIO      |    0 |     0 |          0 |        20 |  0.00 |
-| MMCME2_ADV |    0 |     0 |          0 |         5 |  0.00 |
-| PLLE2_ADV  |    0 |     0 |          0 |         5 |  0.00 |
-| BUFMRCE    |    0 |     0 |          0 |        10 |  0.00 |
-| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
-| BUFR       |    0 |     0 |          0 |        20 |  0.00 |
-+------------+------+-------+------------+-----------+-------+
-
-
-7. Specific Feature
--------------------
-
-+-------------+------+-------+------------+-----------+-------+
-|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
-+-------------+------+-------+------------+-----------+-------+
-| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
-| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
-| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
-| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
-| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
-| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
-| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
-| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
-| XADC        |    0 |     0 |          0 |         1 |  0.00 |
-+-------------+------+-------+------------+-----------+-------+
-
-
-8. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| IBUF     |    2 |                  IO |
-| OBUF     |    1 |                  IO |
-| FDRE     |    1 |        Flop & Latch |
-| BUFG     |    1 |               Clock |
-+----------+------+---------------------+
-
-
-9. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-10. Instantiated Netlists
--------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou
deleted file mode 100644
index 6e5c8e6..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:31:01 2026
-# Process ID         : 287718
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1
-# Command line       : vivado -log soc.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source soc.tcl -notrace
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/soc.vdi
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 4069.591 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3633 MB
-#-----------------------------------------------------------
-source soc.tcl -notrace
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.pb
deleted file mode 100644
index d56aa35..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/vivado.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/write_bitstream.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/write_bitstream.pb
deleted file mode 100644
index 5072602..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/impl_1/write_bitstream.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Vivado_Synthesis.queue.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Vivado_Synthesis.queue.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Vivado_Synthesis.queue.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Xil/soc_propImpl.xdc b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Xil/soc_propImpl.xdc
deleted file mode 100644
index 6325114..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.Xil/soc_propImpl.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_property SRC_FILE_INFO {cfile:/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc rfile:../../../AT-0000LI02.srcs/constrs_1/new/constraints.xdc id:1} [current_design]
-set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN W5 [get_ports refclk_i]
-set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN A14 [get_ports pwr_good_o]
-set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
-set_property PACKAGE_PIN A15 [get_ports reset_ni]
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.begin.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.begin.rst
deleted file mode 100644
index f4ee686..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.begin.rst
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0"?>
-<ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="imar" Host="IRON-B" Pid="287453" HostCore="4" HostMemory="7980808">
-    </Process>
-</ProcessHandle>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.end.rst b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.end.rst
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/.vivado.end.rst
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.js b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.js
deleted file mode 100755
index 61806d0..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.js
+++ /dev/null
@@ -1,270 +0,0 @@
-//
-//  Vivado(TM)
-//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
-//  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
-//  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
-//
-
-// GLOBAL VARIABLES
-var ISEShell = new ActiveXObject( "WScript.Shell" );
-var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
-var ISERunDir = "";
-var ISELogFile = "runme.log";
-var ISELogFileStr = null;
-var ISELogEcho = true;
-var ISEOldVersionWSH = false;
-
-
-
-// BOOTSTRAP
-ISEInit();
-
-
-
-//
-// ISE FUNCTIONS
-//
-function ISEInit() {
-
-  // 1. RUN DIR setup
-  var ISEScrFP = WScript.ScriptFullName;
-  var ISEScrN = WScript.ScriptName;
-  ISERunDir = 
-    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
-
-  // 2. LOG file setup
-  ISELogFileStr = ISEOpenFile( ISELogFile );
-
-  // 3. LOG echo?
-  var ISEScriptArgs = WScript.Arguments;
-  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
-    if ( ISEScriptArgs(loopi) == "-quiet" ) {
-      ISELogEcho = false;
-      break;
-    }
-  }
-
-  // 4. WSH version check
-  var ISEOptimalVersionWSH = 5.6;
-  var ISECurrentVersionWSH = WScript.Version;
-  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
-
-    ISEStdErr( "" );
-    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
-	       ISEOptimalVersionWSH + " or higher. Downloads" );
-    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
-    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
-    ISEStdErr( "" );
-
-    ISEOldVersionWSH = true;
-  }
-
-}
-
-function ISEStep( ISEProg, ISEArgs ) {
-
-  // CHECK for a STOP FILE
-  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
-    ISEStdErr( "" );
-    ISEStdErr( "*** Halting run - EA reset detected ***" );
-    ISEStdErr( "" );
-    WScript.Quit( 1 );
-  }
-
-  // WRITE STEP HEADER to LOG
-  ISEStdOut( "" );
-  ISEStdOut( "*** Running " + ISEProg );
-  ISEStdOut( "    with args " + ISEArgs );
-  ISEStdOut( "" );
-
-  // LAUNCH!
-  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
-  if ( ISEExitCode != 0 ) {
-    WScript.Quit( ISEExitCode );
-  }
-
-}
-
-function ISEExec( ISEProg, ISEArgs ) {
-
-  var ISEStep = ISEProg;
-  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
-    ISEProg += ".bat";
-  }
-
-  var ISECmdLine = ISEProg + " " + ISEArgs;
-  var ISEExitCode = 1;
-
-  if ( ISEOldVersionWSH ) { // WSH 5.1
-
-    // BEGIN file creation
-    ISETouchFile( ISEStep, "begin" );
-
-    // LAUNCH!
-    ISELogFileStr.Close();
-    ISECmdLine = 
-      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
-    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
-    ISELogFileStr = ISEOpenFile( ISELogFile );
-
-  } else {  // WSH 5.6
-
-    // LAUNCH!
-    ISEShell.CurrentDirectory = ISERunDir;
-
-    // Redirect STDERR to STDOUT
-    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
-    var ISEProcess = ISEShell.Exec( ISECmdLine );
-    
-    // BEGIN file creation
-    var wbemFlagReturnImmediately = 0x10;
-    var wbemFlagForwardOnly = 0x20;
-    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
-    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
-    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
-    var NOC = 0;
-    var NOLP = 0;
-    var TPM = 0;
-    var cpuInfos = new Enumerator(processor);
-    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
-        var cpuInfo = cpuInfos.item();
-        NOC += cpuInfo.NumberOfCores;
-        NOLP += cpuInfo.NumberOfLogicalProcessors;
-    }
-    var csInfos = new Enumerator(computerSystem);
-    for(;!csInfos.atEnd(); csInfos.moveNext()) {
-        var csInfo = csInfos.item();
-        TPM += csInfo.TotalPhysicalMemory;
-    }
-
-    var ISEHOSTCORE = NOLP
-    var ISEMEMTOTAL = TPM
-
-    var ISENetwork = WScript.CreateObject( "WScript.Network" );
-    var ISEHost = ISENetwork.ComputerName;
-    var ISEUser = ISENetwork.UserName;
-    var ISEPid = ISEProcess.ProcessID;
-    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
-    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
-    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
-    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
-			    "\" Owner=\"" + ISEUser + 
-			    "\" Host=\"" + ISEHost + 
-			    "\" Pid=\"" + ISEPid +
-			    "\" HostCore=\"" + ISEHOSTCORE +
-			    "\" HostMemory=\"" + ISEMEMTOTAL +
-			    "\">" );
-    ISEBeginFile.WriteLine( "    </Process>" );
-    ISEBeginFile.WriteLine( "</ProcessHandle>" );
-    ISEBeginFile.Close();
-    
-    var ISEOutStr = ISEProcess.StdOut;
-    var ISEErrStr = ISEProcess.StdErr;
-    
-    // WAIT for ISEStep to finish
-    while ( ISEProcess.Status == 0 ) {
-      
-      // dump stdout then stderr - feels a little arbitrary
-      while ( !ISEOutStr.AtEndOfStream ) {
-        ISEStdOut( ISEOutStr.ReadLine() );
-      }  
-      
-      WScript.Sleep( 100 );
-    }
-
-    ISEExitCode = ISEProcess.ExitCode;
-  }
-
-  ISELogFileStr.Close();
-
-  // END/ERROR file creation
-  if ( ISEExitCode != 0 ) {    
-    ISETouchFile( ISEStep, "error" );
-    
-  } else {
-    ISETouchFile( ISEStep, "end" );
-  }
-
-  return ISEExitCode;
-}
-
-
-//
-// UTILITIES
-//
-function ISEStdOut( ISELine ) {
-
-  ISELogFileStr.WriteLine( ISELine );
-  
-  if ( ISELogEcho ) {
-    WScript.StdOut.WriteLine( ISELine );
-  }
-}
-
-function ISEStdErr( ISELine ) {
-  
-  ISELogFileStr.WriteLine( ISELine );
-
-  if ( ISELogEcho ) {
-    WScript.StdErr.WriteLine( ISELine );
-  }
-}
-
-function ISETouchFile( ISERoot, ISEStatus ) {
-
-  var ISETFile = 
-    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
-  ISETFile.Close();
-}
-
-function ISEOpenFile( ISEFilename ) {
-
-  // This function has been updated to deal with a problem seen in CR #870871.
-  // In that case the user runs a script that runs impl_1, and then turns around
-  // and runs impl_1 -to_step write_bitstream. That second run takes place in
-  // the same directory, which means we may hit some of the same files, and in
-  // particular, we will open the runme.log file. Even though this script closes
-  // the file (now), we see cases where a subsequent attempt to open the file
-  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
-  // play? In any case, we try to work around this by first waiting if the file
-  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
-  // and try to open the file 10 times with a one second delay after each attempt.
-  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
-  // If there is an unrecognized exception when trying to open the file, we output
-  // an error message and write details to an exception.log file.
-  var ISEFullPath = ISERunDir + "/" + ISEFilename;
-  if (ISEFileSys.FileExists(ISEFullPath)) {
-    // File is already there. This could be a problem. Wait in case it is still in use.
-    WScript.Sleep(5000);
-  }
-  var i;
-  for (i = 0; i < 10; ++i) {
-    try {
-      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
-    } catch (exception) {
-      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
-      if (error_code == 52) { // 52 is bad file name or number.
-        // Wait a second and try again.
-        WScript.Sleep(1000);
-        continue;
-      } else {
-        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
-        var exceptionFilePath = ISERunDir + "/exception.log";
-        if (!ISEFileSys.FileExists(exceptionFilePath)) {
-          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
-          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
-          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
-          exceptionFile.WriteLine("\tException name: " + exception.name);
-          exceptionFile.WriteLine("\tException error code: " + error_code);
-          exceptionFile.WriteLine("\tException message: " + exception.message);
-          exceptionFile.Close();
-        }
-        throw exception;
-      }
-    }
-  }
-  // If we reached this point, we failed to open the file after 10 attempts.
-  // We need to error out.
-  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
-  WScript.Quit(1);
-}
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.sh
deleted file mode 100755
index e085d18..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/ISEWrap.sh
+++ /dev/null
@@ -1,85 +0,0 @@
-#!/bin/bash
-
-#
-#  Vivado(TM)
-#  ISEWrap.sh: Vivado Runs Script for UNIX
-#  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
-#  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
-#
-
-cmd_exists()
-{
-  command -v "$1" >/dev/null 2>&1
-}
-
-HD_LOG=$1
-shift
-
-# CHECK for a STOP FILE
-if [ -f .stop.rst ]
-then
-echo ""                                        >> $HD_LOG
-echo "*** Halting run - EA reset detected ***" >> $HD_LOG
-echo ""                                        >> $HD_LOG
-exit 1
-fi
-
-ISE_STEP=$1
-shift
-
-# WRITE STEP HEADER to LOG
-echo ""                      >> $HD_LOG
-echo "*** Running $ISE_STEP" >> $HD_LOG
-echo "    with args $@"      >> $HD_LOG
-echo ""                      >> $HD_LOG
-
-# LAUNCH!
-$ISE_STEP "$@" >> $HD_LOG 2>&1 &
-
-# BEGIN file creation
-ISE_PID=$!
-
-HostNameFile=/proc/sys/kernel/hostname
-if cmd_exists hostname
-then
-ISE_HOST=$(hostname)
-elif cmd_exists uname
-then
-ISE_HOST=$(uname -n)
-elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
-then
-ISE_HOST=$(cat $HostNameFile)
-elif [ X != X$HOSTNAME ]
-then
-ISE_HOST=$HOSTNAME #bash
-else
-ISE_HOST=$HOST     #csh
-fi
-
-ISE_USER=$USER
-
-ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
-ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
-
-ISE_BEGINFILE=.$ISE_STEP.begin.rst
-/bin/touch $ISE_BEGINFILE
-echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
-echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
-echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
-echo "    </Process>"                                                                              >> $ISE_BEGINFILE
-echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
-
-# WAIT for ISEStep to finish
-wait $ISE_PID
-
-# END/ERROR file creation
-RETVAL=$?
-if [ $RETVAL -eq 0 ]
-then
-    /bin/touch .$ISE_STEP.end.rst
-else
-    /bin/touch .$ISE_STEP.error.rst
-fi
-
-exit $RETVAL
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/__synthesis_is_complete__ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/__synthesis_is_complete__
deleted file mode 100644
index e69de29..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/__synthesis_is_complete__
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/gen_run.xml b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/gen_run.xml
deleted file mode 100644
index 9e54b0f..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/gen_run.xml
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1790371817">
-  <File Type="VDS-TIMINGSUMMARY" Name="soc_timing_summary_synth.rpt"/>
-  <File Type="RDS-DCP" Name="soc.dcp"/>
-  <File Type="RDS-UTIL-PB" Name="soc_utilization_synth.pb"/>
-  <File Type="RDS-UTIL" Name="soc_utilization_synth.rpt"/>
-  <File Type="RDS-PROPCONSTRS" Name="soc_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="soc.vds"/>
-  <File Type="REPORTS-TCL" Name="soc_reports.tcl"/>
-  <File Type="VDS-TIMING-PB" Name="soc_timing_summary_synth.pb"/>
-  <File Type="PA-TCL" Name="soc.tcl"/>
-  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
-    <Filter Type="Srcs"/>
-    <File Path="$PPRDIR/../../../../rtl/soc.sv">
-      <FileInfo>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
-        <Attr Name="UsedIn" Val="simulation"/>
-      </FileInfo>
-    </File>
-    <Config>
-      <Option Name="DesignMode" Val="RTL"/>
-      <Option Name="TopModule" Val="soc"/>
-      <Option Name="TopAutoSet" Val="TRUE"/>
-    </Config>
-  </FileSet>
-  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
-    <Filter Type="Constrs"/>
-    <File Path="$PSRCDIR/constrs_1/new/constraints.xdc">
-      <FileInfo>
-        <Attr Name="UsedIn" Val="synthesis"/>
-        <Attr Name="UsedIn" Val="implementation"/>
-      </FileInfo>
-    </File>
-    <Config>
-      <Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/constraints.xdc"/>
-      <Option Name="ConstrsType" Val="XDC"/>
-    </Config>
-  </FileSet>
-  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
-    <Filter Type="Utils"/>
-    <Config>
-      <Option Name="TopAutoSet" Val="TRUE"/>
-    </Config>
-  </FileSet>
-  <Strategy Version="1" Minor="2">
-    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2026">
-      <Desc>Vivado Synthesis Defaults</Desc>
-    </StratHandle>
-    <Step Id="synth_design"/>
-  </Strategy>
-</GenRun>
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/htr.txt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/htr.txt
deleted file mode 100644
index e24be3d..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/htr.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Vivado(TM)
-# htr.txt: a Vivado-generated description of how-to-repeat the
-#          the basic steps of a run.  Note that runme.bat/sh needs
-#          to be invoked for Vivado to track run status.
-# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-#
-
-vivado -log soc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/rundef.js b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/rundef.js
deleted file mode 100644
index a4c68bf..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/rundef.js
+++ /dev/null
@@ -1,41 +0,0 @@
-//
-// Vivado(TM)
-// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
-// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-// Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-//
-
-echo "This script was generated under a different operating system."
-echo "Please update the PATH variable below, before executing this script"
-exit
-
-var WshShell = new ActiveXObject( "WScript.Shell" );
-var ProcEnv = WshShell.Environment( "Process" );
-var PathVal = ProcEnv("PATH");
-if ( PathVal.length == 0 ) {
-  PathVal = "/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64;/home/imar/vivado/2026.1/Vivado/bin;";
-} else {
-  PathVal = "/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64;/home/imar/vivado/2026.1/Vivado/bin;" + PathVal;
-}
-
-ProcEnv("PATH") = PathVal;
-
-var RDScrFP = WScript.ScriptFullName;
-var RDScrN = WScript.ScriptName;
-var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
-var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
-eval( EAInclude(ISEJScriptLib) );
-
-
-ISEStep( "vivado",
-         "-log soc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl" );
-
-
-
-function EAInclude( EAInclFilename ) {
-  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
-  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
-  var EAIFContents = EAInclFile.ReadAll();
-  EAInclFile.Close();
-  return EAIFContents;
-}
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.bat b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.bat
deleted file mode 100644
index 829dfd8..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.bat
+++ /dev/null
@@ -1,12 +0,0 @@
-@echo off
-
-rem  Vivado (TM)
-rem  runme.bat: a Vivado-generated Script
-rem  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-rem  Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-
-set HD_SDIR=%~dp0
-cd /d "%HD_SDIR%"
-set PATH=%SYSTEMROOT%\system32;%PATH%
-cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.log b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.log
deleted file mode 100644
index bf9d466..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.log
+++ /dev/null
@@ -1,233 +0,0 @@
-
-*** Running vivado
-    with args -log soc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
-
-INFO: [Common 17-3922] A valid Vivado Design Suite BASIC license has been detected. Your current license is active and will expire on 25-sep-2027.
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:30:20 2026
-# Process ID         : 287507
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1
-# Command line       : vivado -log soc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 3937.630 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3428 MB
-#-----------------------------------------------------------
-
-****** Vivado v2026.1 (64-bit)
-  **** SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-  **** IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-  **** SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-  **** Start of session at: Fri Sep 25 21:30:20 2026
-    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-    ** Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-
-source soc.tcl -notrace
-Command: synth_design -top soc -part xc7a35tcpg236-1
-Starting synth_design
-Attempting to get a license for feature 'Vivado_Synthesis' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Synthesis' and/or device 'xc7a35t'
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-INFO: [Designutils 20-5008] Incremental synthesis strategy default
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 287545
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2383.734 ; gain = 517.148 ; free physical = 256 ; free virtual = 2198
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'soc' [/home/imar/Lab/silicon/AT-0000LI02/rtl/soc.sv:13]
-INFO: [Synth 8-6155] done synthesizing module 'soc' (0#1) [/home/imar/Lab/silicon/AT-0000LI02/rtl/soc.sv:13]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2470.703 ; gain = 604.117 ; free physical = 364 ; free virtual = 2021
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2485.547 ; gain = 618.961 ; free physical = 518 ; free virtual = 2051
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2485.547 ; gain = 618.961 ; free physical = 518 ; free virtual = 2051
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2485.547 ; gain = 0.000 ; free physical = 452 ; free virtual = 2052
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-Finished Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/soc_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/soc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2606.480 ; gain = 0.000 ; free physical = 485 ; free virtual = 2007
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2606.516 ; gain = 0.000 ; free physical = 474 ; free virtual = 2000
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2606.516 ; gain = 739.930 ; free physical = 505 ; free virtual = 2090
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7a35tcpg236-1
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 504 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 504 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 502 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Component Statistics 
----------------------------------------------------------------------------------
-Detailed RTL Component Info : 
-+---Registers : 
-	                1 Bit    Registers := 1     
----------------------------------------------------------------------------------
-Finished RTL Component Statistics 
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 90 (col length:60)
-BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 488 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2733.484 ; gain = 866.898 ; free physical = 338 ; free virtual = 1956
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2733.484 ; gain = 866.898 ; free physical = 338 ; free virtual = 1956
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2743.500 ; gain = 876.914 ; free physical = 335 ; free virtual = 1945
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes: 
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage: 
-+------+-----+------+
-|      |Cell |Count |
-+------+-----+------+
-|1     |BUFG |     1|
-|2     |FDRE |     1|
-|3     |IBUF |     2|
-|4     |OBUF |     1|
-+------+-----+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2949.312 ; gain = 961.758 ; free physical = 178 ; free virtual = 1764
-Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.320 ; gain = 1082.727 ; free physical = 177 ; free virtual = 1765
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2949.320 ; gain = 0.000 ; free physical = 131 ; free virtual = 1772
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2949.320 ; gain = 0.000 ; free physical = 274 ; free virtual = 1945
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Synth Design complete | Checksum: 793f5413
-INFO: [Common 17-83] Releasing license: Vivado_Synthesis
-16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 2949.348 ; gain = 1161.965 ; free physical = 255 ; free virtual = 1933
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1704.190; main = 1704.190; forked = 272.542
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3704.191; main = 2949.316; forked = 1048.703
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2997.324 ; gain = 0.000 ; free physical = 246 ; free virtual = 1932
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp' has been generated.
-INFO: [Vivado 12-24828] Executing command : report_utilization -file soc_utilization_synth.rpt -pb soc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri Sep 25 21:30:59 2026...
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.sh b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.sh
deleted file mode 100755
index e46f2fb..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/runme.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/bash
-
-# 
-# Vivado(TM)
-# runme.sh: a Vivado-generated Runs Script for UNIX
-# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-# Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
-# 
-
-if [ -z "$PATH" ]; then
-  PATH=/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64:/home/imar/vivado/2026.1/Vivado/bin
-else
-  PATH=/home/imar/vivado/2026.1/Vitis/bin:/home/imar/vivado/2026.1/Vivado/ids_lite/ISE/bin/lin64:/home/imar/vivado/2026.1/Vivado/bin:$PATH
-fi
-export PATH
-
-if [ -z "$LD_LIBRARY_PATH" ]; then
-  LD_LIBRARY_PATH=
-else
-  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
-fi
-export LD_LIBRARY_PATH
-
-HD_PWD='/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1'
-cd "$HD_PWD"
-
-HD_LOG=runme.log
-/bin/touch $HD_LOG
-
-ISEStep="./ISEWrap.sh"
-EAStep()
-{
-     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
-     if [ $? -ne 0 ]
-     then
-         exit
-     fi
-}
-
-EAStep vivado -log soc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp
deleted file mode 100644
index 450e915..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.tcl b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.tcl
deleted file mode 100644
index 90c0288..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.tcl
+++ /dev/null
@@ -1,110 +0,0 @@
-# 
-# Synthesis run script generated by Vivado
-# 
-
-set TIME_start [clock seconds] 
-namespace eval ::optrace {
-  variable script "/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.tcl"
-  variable category "vivado_synth"
-}
-
-# Try to connect to running dispatch if we haven't done so already.
-# This code assumes that the Tcl interpreter is not using threads,
-# since the ::dispatch::connected variable isn't mutex protected.
-if {![info exists ::dispatch::connected]} {
-  namespace eval ::dispatch {
-    variable connected false
-    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
-      set result "true"
-      if {[catch {
-        if {[lsearch -exact [package names] DispatchTcl] < 0} {
-          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
-        }
-        if {$result eq "false"} {
-          puts "WARNING: Could not load dispatch client library"
-        }
-        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
-        if { $connect_id eq "" } {
-          puts "WARNING: Could not initialize dispatch client"
-        } else {
-          puts "INFO: Dispatch client connection id - $connect_id"
-          set connected true
-        }
-      } catch_res]} {
-        puts "WARNING: failed to connect to dispatch server - $catch_res"
-      }
-    }
-  }
-}
-if {$::dispatch::connected} {
-  # Remove the dummy proc if it exists.
-  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
-    rename ::OPTRACE ""
-  }
-  proc ::OPTRACE { task action {tags {} } } {
-    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
-  }
-  # dispatch is generic. We specifically want to attach logging.
-  ::vitis_log::connect_client
-} else {
-  # Add dummy proc if it doesn't exist.
-  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
-    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
-        # Do nothing
-    }
-  }
-}
-
-OPTRACE "synth_1" START { ROLLUP_AUTO }
-set_param chipscope.maxJobs 1
-set_param xicom.use_bs_reader 1
-set_param general.usePosixSpawnForFork 1
-OPTRACE "Creating in-memory project" START { }
-create_project -in_memory -part xc7a35tcpg236-1
-
-set_param project.singleFileAddWarning.threshold 0
-set_param project.compositeFile.enableAutoGeneration 0
-set_param synth.vivado.isSynthRun true
-set_property webtalk.parent_dir /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/wt [current_project]
-set_property parent.project_path /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr [current_project]
-set_property default_lib xil_defaultlib [current_project]
-set_property target_language Verilog [current_project]
-set_property ip_output_repo /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.cache/ip [current_project]
-set_property ip_cache_permissions {read write} [current_project]
-OPTRACE "Creating in-memory project" END { }
-OPTRACE "Adding files" START { }
-read_verilog -library xil_defaultlib -sv /home/imar/Lab/silicon/AT-0000LI02/rtl/soc.sv
-OPTRACE "Adding files" END { }
-# Mark all dcp files as not used in implementation to prevent them from being
-# stitched into the results of this synthesis run. Any black boxes in the
-# design are intentionally left as such for best results. Dcp files will be
-# stitched into the design at a later time, either when this synthesis run is
-# opened, or when it is stitched into a dependent implementation run.
-foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
-  set_property used_in_implementation false $dcp
-}
-read_xdc /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc
-set_property used_in_implementation false [get_files /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-
-set_param ips.enableIPCacheLiteLoad 1
-close [open __synthesis_is_running__ w]
-
-OPTRACE "synth_design" START { }
-synth_design -top soc -part xc7a35tcpg236-1
-OPTRACE "synth_design" END { }
-if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
- send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
-}
-
-
-OPTRACE "write_checkpoint" START { CHECKPOINT }
-# disable binary constraint mode for synth run checkpoints
-set_param constraints.enableBinaryConstraints false
-write_checkpoint -force -noxdef soc.dcp
-OPTRACE "write_checkpoint" END { }
-OPTRACE "synth reports" START { REPORT }
-generate_parallel_reports -reports { "report_utilization -file soc_utilization_synth.rpt -pb soc_utilization_synth.pb"  } 
-OPTRACE "synth reports" END { }
-file delete __synthesis_is_running__
-close [open __synthesis_is_complete__ w]
-OPTRACE "synth_1" END { }
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds
deleted file mode 100644
index 6504416..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds
+++ /dev/null
@@ -1,220 +0,0 @@
-INFO: [Common 17-3922] A valid Vivado Design Suite BASIC license has been detected. Your current license is active and will expire on 25-sep-2027.
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:30:20 2026
-# Process ID         : 287507
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1
-# Command line       : vivado -log soc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 3937.630 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3428 MB
-#-----------------------------------------------------------
-source soc.tcl -notrace
-Command: synth_design -top soc -part xc7a35tcpg236-1
-Starting synth_design
-Attempting to get a license for feature 'Vivado_Synthesis' and/or device 'xc7a35t'
-INFO: [Common 17-349] Got license for feature 'Vivado_Synthesis' and/or device 'xc7a35t'
-INFO: [Device 21-403] Loading part xc7a35tcpg236-1
-INFO: [Designutils 20-5008] Incremental synthesis strategy default
-INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
-INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 287545
----------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2383.734 ; gain = 517.148 ; free physical = 256 ; free virtual = 2198
----------------------------------------------------------------------------------
-INFO: [Synth 8-6157] synthesizing module 'soc' [/home/imar/Lab/silicon/AT-0000LI02/rtl/soc.sv:13]
-INFO: [Synth 8-6155] done synthesizing module 'soc' (0#1) [/home/imar/Lab/silicon/AT-0000LI02/rtl/soc.sv:13]
----------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2470.703 ; gain = 604.117 ; free physical = 364 ; free virtual = 2021
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2485.547 ; gain = 618.961 ; free physical = 518 ; free virtual = 2051
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2485.547 ; gain = 618.961 ; free physical = 518 ; free virtual = 2051
----------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2485.547 ; gain = 0.000 ; free physical = 452 ; free virtual = 2052
-INFO: [Project 1-570] Preparing netlist for logic optimization
-
-Processing XDC Constraints
-Initializing timing engine
-Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-Finished Parsing XDC File [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]
-INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/constrs_1/new/constraints.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/soc_propImpl.xdc].
-Resolution: To avoid this warning, move constraints listed in [.Xil/soc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
-Completed Processing XDC Constraints
-
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2606.480 ; gain = 0.000 ; free physical = 485 ; free virtual = 2007
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2606.516 ; gain = 0.000 ; free physical = 474 ; free virtual = 2000
----------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2606.516 ; gain = 739.930 ; free physical = 505 ; free virtual = 2090
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Loading Part and Timing Information
----------------------------------------------------------------------------------
-Loading part: xc7a35tcpg236-1
----------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 504 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying 'set_property' XDC Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 504 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 502 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start RTL Component Statistics 
----------------------------------------------------------------------------------
-Detailed RTL Component Info : 
-+---Registers : 
-	                1 Bit    Registers := 1     
----------------------------------------------------------------------------------
-Finished RTL Component Statistics 
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Part Resource Summary
----------------------------------------------------------------------------------
-Part Resources:
-DSPs: 90 (col length:60)
-BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
----------------------------------------------------------------------------------
-Finished Part Resource Summary
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Cross Boundary and Area Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2622.484 ; gain = 755.898 ; free physical = 488 ; free virtual = 2091
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Applying XDC Timing Constraints
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2733.484 ; gain = 866.898 ; free physical = 338 ; free virtual = 1956
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Timing Optimization
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2733.484 ; gain = 866.898 ; free physical = 338 ; free virtual = 1956
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Technology Mapping
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2743.500 ; gain = 876.914 ; free physical = 335 ; free virtual = 1945
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Flattening Before IO Insertion
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Final Netlist Cleanup
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Instances
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Rebuilding User Hierarchy
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Ports
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Handling Custom Attributes
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Renaming Generated Nets
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-Start Writing Synthesis Report
----------------------------------------------------------------------------------
-
-Report BlackBoxes: 
-+-+--------------+----------+
-| |BlackBox name |Instances |
-+-+--------------+----------+
-+-+--------------+----------+
-
-Report Cell Usage: 
-+------+-----+------+
-|      |Cell |Count |
-+------+-----+------+
-|1     |BUFG |     1|
-|2     |FDRE |     1|
-|3     |IBUF |     2|
-|4     |OBUF |     1|
-+------+-----+------+
----------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.312 ; gain = 1082.727 ; free physical = 178 ; free virtual = 1764
----------------------------------------------------------------------------------
-Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2949.312 ; gain = 961.758 ; free physical = 178 ; free virtual = 1764
-Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2949.320 ; gain = 1082.727 ; free physical = 177 ; free virtual = 1765
-INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2949.320 ; gain = 0.000 ; free physical = 131 ; free virtual = 1772
-INFO: [Project 1-570] Preparing netlist for logic optimization
-INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2949.320 ; gain = 0.000 ; free physical = 274 ; free virtual = 1945
-INFO: [Project 1-111] Unisim Transformation Summary:
-No Unisim elements were transformed.
-
-Synth Design complete | Checksum: 793f5413
-INFO: [Common 17-83] Releasing license: Vivado_Synthesis
-16 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
-synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 2949.348 ; gain = 1161.965 ; free physical = 255 ; free virtual = 1933
-INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1704.190; main = 1704.190; forked = 272.542
-INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3704.191; main = 2949.316; forked = 1048.703
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2997.324 ; gain = 0.000 ; free physical = 246 ; free virtual = 1932
-INFO: [Common 17-1381] The checkpoint '/home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.dcp' has been generated.
-INFO: [Vivado 12-24828] Executing command : report_utilization -file soc_utilization_synth.rpt -pb soc_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Fri Sep 25 21:30:59 2026...
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.pb
deleted file mode 100644
index fd6ee0b..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.rpt b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.rpt
deleted file mode 100644
index 137e9eb..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc_utilization_synth.rpt
+++ /dev/null
@@ -1,179 +0,0 @@
-Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2026 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------
-| Tool Version : Vivado v.2026.1 (lin64) Build 6511674 Tue Jun 16 11:01:26 MDT 2026
-| Date         : Fri Sep 25 21:30:59 2026
-| Host         : IRON-B running 64-bit unknown
-| Command      : report_utilization -file soc_utilization_synth.rpt -pb soc_utilization_synth.pb
-| Design       : soc
-| Device       : xc7a35tcpg236-1
-| Speed File   : -1
-| Design State : Synthesized
----------------------------------------------------------------------------------------------------------------------------------------------
-
-Utilization Design Information
-
-Table of Contents
------------------
-1. Slice Logic
-1.1 Summary of Registers by Type
-2. Memory
-3. DSP
-4. IO and GT Specific
-5. Clocking
-6. Specific Feature
-7. Primitives
-8. Black Boxes
-9. Instantiated Netlists
-
-1. Slice Logic
---------------
-
-+-------------------------+------+-------+------------+-----------+-------+
-|        Site Type        | Used | Fixed | Prohibited | Available | Util% |
-+-------------------------+------+-------+------------+-----------+-------+
-| Slice LUTs*             |    0 |     0 |          0 |     20800 |  0.00 |
-|   LUT as Logic          |    0 |     0 |          0 |     20800 |  0.00 |
-|   LUT as Memory         |    0 |     0 |          0 |      9600 |  0.00 |
-| Slice Registers         |    1 |     0 |          0 |     41600 | <0.01 |
-|   Register as Flip Flop |    1 |     0 |          0 |     41600 | <0.01 |
-|   Register as Latch     |    0 |     0 |          0 |     41600 |  0.00 |
-| F7 Muxes                |    0 |     0 |          0 |     16300 |  0.00 |
-| F8 Muxes                |    0 |     0 |          0 |      8150 |  0.00 |
-| Unique Control Sets     |    1 |       |          0 |      8150 |  0.01 |
-+-------------------------+------+-------+------------+-----------+-------+
-* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
-Warning! LUT value is adjusted to account for LUT combining.
-Warning! For any ECO changes, please run place_design if there are unplaced instances
-** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
-
-
-1.1 Summary of Registers by Type
---------------------------------
-
-+-------+--------------+-------------+--------------+
-| Total | Clock Enable | Synchronous | Asynchronous |
-+-------+--------------+-------------+--------------+
-| 0     |            _ |           - |            - |
-| 0     |            _ |           - |          Set |
-| 0     |            _ |           - |        Reset |
-| 0     |            _ |         Set |            - |
-| 0     |            _ |       Reset |            - |
-| 0     |          Yes |           - |            - |
-| 0     |          Yes |           - |          Set |
-| 0     |          Yes |           - |        Reset |
-| 0     |          Yes |         Set |            - |
-| 1     |          Yes |       Reset |            - |
-+-------+--------------+-------------+--------------+
-
-
-2. Memory
----------
-
-+----------------+------+-------+------------+-----------+-------+
-|    Site Type   | Used | Fixed | Prohibited | Available | Util% |
-+----------------+------+-------+------------+-----------+-------+
-| Block RAM Tile |    0 |     0 |          0 |        50 |  0.00 |
-|   RAMB36/FIFO* |    0 |     0 |          0 |        50 |  0.00 |
-|   RAMB18       |    0 |     0 |          0 |       100 |  0.00 |
-+----------------+------+-------+------------+-----------+-------+
-* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
-
-
-3. DSP
-------
-
-+-----------+------+-------+------------+-----------+-------+
-| Site Type | Used | Fixed | Prohibited | Available | Util% |
-+-----------+------+-------+------------+-----------+-------+
-| DSPs      |    0 |     0 |          0 |        90 |  0.00 |
-+-----------+------+-------+------------+-----------+-------+
-
-
-4. IO and GT Specific
----------------------
-
-+-----------------------------+------+-------+------------+-----------+-------+
-|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
-+-----------------------------+------+-------+------------+-----------+-------+
-| Bonded IOB                  |    3 |     0 |          0 |       106 |  2.83 |
-| Bonded IPADs                |    0 |     0 |          0 |        10 |  0.00 |
-| Bonded OPADs                |    0 |     0 |          0 |         4 |  0.00 |
-| PHY_CONTROL                 |    0 |     0 |          0 |         5 |  0.00 |
-| PHASER_REF                  |    0 |     0 |          0 |         5 |  0.00 |
-| OUT_FIFO                    |    0 |     0 |          0 |        20 |  0.00 |
-| IN_FIFO                     |    0 |     0 |          0 |        20 |  0.00 |
-| IDELAYCTRL                  |    0 |     0 |          0 |         5 |  0.00 |
-| IBUFDS                      |    0 |     0 |          0 |       104 |  0.00 |
-| GTPE2_CHANNEL               |    0 |     0 |          0 |         2 |  0.00 |
-| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        20 |  0.00 |
-| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        20 |  0.00 |
-| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |          0 |       250 |  0.00 |
-| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
-| ILOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
-| OLOGIC                      |    0 |     0 |          0 |       106 |  0.00 |
-+-----------------------------+------+-------+------------+-----------+-------+
-
-
-5. Clocking
------------
-
-+------------+------+-------+------------+-----------+-------+
-|  Site Type | Used | Fixed | Prohibited | Available | Util% |
-+------------+------+-------+------------+-----------+-------+
-| BUFGCTRL   |    1 |     0 |          0 |        32 |  3.13 |
-| BUFIO      |    0 |     0 |          0 |        20 |  0.00 |
-| MMCME2_ADV |    0 |     0 |          0 |         5 |  0.00 |
-| PLLE2_ADV  |    0 |     0 |          0 |         5 |  0.00 |
-| BUFMRCE    |    0 |     0 |          0 |        10 |  0.00 |
-| BUFHCE     |    0 |     0 |          0 |        72 |  0.00 |
-| BUFR       |    0 |     0 |          0 |        20 |  0.00 |
-+------------+------+-------+------------+-----------+-------+
-
-
-6. Specific Feature
--------------------
-
-+-------------+------+-------+------------+-----------+-------+
-|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
-+-------------+------+-------+------------+-----------+-------+
-| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
-| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
-| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
-| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
-| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
-| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
-| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
-| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
-| XADC        |    0 |     0 |          0 |         1 |  0.00 |
-+-------------+------+-------+------------+-----------+-------+
-
-
-7. Primitives
--------------
-
-+----------+------+---------------------+
-| Ref Name | Used | Functional Category |
-+----------+------+---------------------+
-| IBUF     |    2 |                  IO |
-| OBUF     |    1 |                  IO |
-| FDRE     |    1 |        Flop & Latch |
-| BUFG     |    1 |               Clock |
-+----------+------+---------------------+
-
-
-8. Black Boxes
---------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
-9. Instantiated Netlists
-------------------------
-
-+----------+------+
-| Ref Name | Used |
-+----------+------+
-
-
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou
deleted file mode 100644
index 2c2db33..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou
+++ /dev/null
@@ -1,24 +0,0 @@
-#-----------------------------------------------------------
-# Vivado v2026.1 (64-bit)
-# SW Build 6511674 on Tue Jun 16 11:01:26 MDT 2026
-# IP Build 6504888 on Tue Jun 09 09:05:25 MDT 2026
-# SharedData Build 6501428 on Mon Jun 08 17:34:18 MDT 2026
-# Start of session at: Fri Sep 25 21:30:20 2026
-# Process ID         : 287507
-# Current directory  : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1
-# Command line       : vivado -log soc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source soc.tcl
-# Log file           : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/soc.vds
-# Journal file       : /home/imar/Lab/silicon/AT-0000LI02/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.jou
-# Running On         : IRON-B
-# Platform           : unknown
-# Operating System   : unknown
-# Processor Detail   : Intel(R) Core(TM) i5-7600 CPU @ 3.50GHz
-# CPU Frequency      : 3937.630 MHz
-# CPU Physical cores : 4
-# CPU Logical cores  : 4
-# Host memory        : 8172 MB
-# Swap memory        : 0 MB
-# Total Virtual      : 8172 MB
-# Available Virtual  : 3428 MB
-#-----------------------------------------------------------
-source soc.tcl -notrace
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.pb b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.pb
deleted file mode 100644
index 5fb0aca..0000000
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.runs/synth_1/vivado.pb
+++ /dev/null
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/sources_1/ip/gpll/gpll.xci b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/sources_1/ip/gpll/gpll.xci
new file mode 100644
index 0000000..1ef5d75
--- /dev/null
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.srcs/sources_1/ip/gpll/gpll.xci
@@ -0,0 +1,671 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "gpll",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "19",
+    "gen_directory": "../../../../AT-0000LI02.gen/sources_1/ip/gpll",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "gpll", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "300.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "9", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "111.879", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "105.461", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "gpll", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__300.00000______0.000______50.0______111.879____105.461", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "300.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "300.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "9.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "3.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "PLL", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "300.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "42.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
+        "BASE_BOARD_PART": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "BOARD_CONNECTIONS": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "DEVICE": [ { "value": "xc7a35t", "resolve_type": "generated", "usage": "all" } ],
+        "PACKAGE": [ { "value": "cpg236", "resolve_type": "generated", "usage": "all" } ],
+        "PREFHDL": [ { "value": "VERILOG", "resolve_type": "generated", "usage": "all" } ],
+        "SILICON_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED", "resolve_type": "generated", "usage": "all" } ],
+        "SPEEDGRADE": [ { "value": "-1", "resolve_type": "generated", "usage": "all" } ],
+        "STATIC_POWER": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "TEMPERATURE_GRADE": [ { "value": "", "resolve_type": "generated", "usage": "all" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "19" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../AT-0000LI02.gen/sources_1/ip/gpll" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2026.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "reset": [ { "direction": "in", "driver_value": "0" } ],
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "reset" } ]
+          }
+        },
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        }
+      }
+    }
+  },
+  "checksum": "8dbc8ce2"
+}
+\ No newline at end of file
diff --git a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr
index fe79131..90c633e 100644
--- a/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr
+++ b/board/xilinx/xc7a35tcpg236a/AT-0000LI02/AT-0000LI02.xpr
@@ -75,6 +75,27 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../../../rtl/uncore/clkgen.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../rtl/uncore/north_bridge.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../rtl/uncore/uncore.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../../../../rtl/soc.sv">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -135,6 +156,19 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
+    <FileSet Name="gpll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/gpll" RelGenDir="$PGENDIR/gpll">
+      <File Path="$PSRCDIR/sources_1/ip/gpll/gpll.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="gpll"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -170,6 +204,18 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="gpll_synth_1" Type="Ft3:Synth" SrcSet="gpll" Part="xc7a35tcpg236-1" ConstrsSet="gpll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/gpll_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/gpll_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/gpll_synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2026">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2026"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2026">
@@ -190,6 +236,25 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="gpll_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="gpll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="gpll_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/gpll_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/gpll_impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2026">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2026"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
   <Board/>
   <DashboardSummary Version="1" Minor="0">
author	Ian M. <ian@aptel.org>	2026-09-25 22:39:24 +0000
committer	Ian M. <ian@aptel.org>	2026-09-25 22:39:24 +0000
commit	939ab54f84f2605df494872cde6f1030ea211436 (patch)
tree	5b275002b42d9ceb62b6fbba1fd8f4057eb82b74 /board
parent	f62fb60529f1f7bd9132513d0b39b715d9bdcd25 (diff)