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authorIan M. <ian@patel.org>2026-09-27 21:31:25 +0000
committerIan M. <ian@patel.org>2026-09-27 21:31:25 +0000
commit0dea2c7bc7bb5643aa3b48f2f1310a7a2828f3f9 (patch)
tree025b46e9c9c4babeacc81dced04498ffa0cdebdc /rtl/cpu/cpu_fetch.sv
parent4c0acdb44e26a4b90e1075b4e6d130eb7f5919d4 (diff)
cpu: Add core and fetch unit groundworkmain
Signed-off-by: Ian M. <ian@patel.org>
Diffstat (limited to 'rtl/cpu/cpu_fetch.sv')
-rw-r--r--rtl/cpu/cpu_fetch.sv48
1 files changed, 48 insertions, 0 deletions
diff --git a/rtl/cpu/cpu_fetch.sv b/rtl/cpu/cpu_fetch.sv
new file mode 100644
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+//
+// Copyright (c) 2026, Apollo Telephone Laboratories.
+// Provided under the BSD-3 clause.
+//
+
+`include "bus/ari.svh"
+
+//
+// Represents a CPU fetch
+//
+module cpu_fetch (
+ input wire clk_i,
+ input wire reset_i,
+ input wire memop_done_i,
+
+ output logic mem_req_o,
+ output logic [PMA_XLEN-1:0] mem_ad_o
+);
+ parameter FSM_STAGE_REQUEST = 0;
+ parameter FSM_STAGE_WAIT = 1;
+
+ logic [63:0] pc;
+ logic [2:0] fsm_stage;
+
+ always_ff @(posedge clk_i) begin
+ if (reset_i) begin
+ mem_req_o <= 0;
+ mem_ad_o <= 0;
+ pc <= 0;
+ fsm_stage <= 0;
+ end else begin
+ case (fsm_stage)
+ FSM_STAGE_REQUEST: begin
+ mem_ad_o <= pc;
+ mem_req_o <= 1;
+ fsm_stage <= FSM_STAGE_WAIT;
+ end
+ FSM_STAGE_WAIT: begin
+ if (memop_done_i) begin
+ mem_req_o <= 0;
+ pc <= pc + 4;
+ fsm_stage <= FSM_STAGE_REQUEST;
+ end
+ end
+ endcase
+ end
+ end
+endmodule