cpu: Add core and fetch unit groundworkmain

Signed-off-by: Ian M. <ian@patel.org>

3 files changed, 89 insertions, 1 deletions

diff --git a/rtl/cpu/cpu_core.sv b/rtl/cpu/cpu_core.sv
new file mode 100644
index 0000000..cad1f94
--- /dev/null
+++ b/rtl/cpu/cpu_core.sv
@@ -0,0 +1,32 @@
+//
+// Copyright (c) 2026, Apollo Telephone Laboratories.
+// Provided under the BSD-3 clause.
+//
+
+`include "bus/ari.svh"
+
+//
+// Represents a single processing element
+//
+// @clk_i:          Clock input
+// @reset_i:        Reset input
+// @imc_op_done_i:  IMC operation done
+// @imc_req_o:      IMC request output
+// @imc_ad_o:       IMC address output
+//
+module cpu_core (
+    input wire clk_i,
+    input wire reset_i,
+    input wire imc_op_done_i,
+
+    output logic imc_req_o,
+    output logic [PMA_XLEN-1:0] imc_ad_o
+);
+    cpu_fetch fetch_unit (
+        .clk_i(clk_i),
+        .reset_i(reset_i),
+        .memop_done_i(imc_op_done_i),
+        .mem_req_o(imc_req_o),
+        .mem_ad_o(imc_ad_o)
+    );
+endmodule
diff --git a/rtl/cpu/cpu_fetch.sv b/rtl/cpu/cpu_fetch.sv
new file mode 100644
index 0000000..00fcbd0
--- /dev/null
+++ b/rtl/cpu/cpu_fetch.sv
@@ -0,0 +1,48 @@
+//
+// Copyright (c) 2026, Apollo Telephone Laboratories.
+// Provided under the BSD-3 clause.
+//
+
+`include "bus/ari.svh"
+
+//
+// Represents a CPU fetch
+//
+module cpu_fetch (
+    input wire clk_i,
+    input wire reset_i,
+    input wire memop_done_i,
+
+    output logic mem_req_o,
+    output logic [PMA_XLEN-1:0] mem_ad_o
+);
+    parameter FSM_STAGE_REQUEST   = 0;
+    parameter FSM_STAGE_WAIT      = 1;
+
+    logic [63:0] pc;
+    logic [2:0] fsm_stage;
+
+    always_ff @(posedge clk_i) begin
+        if (reset_i) begin
+            mem_req_o   <= 0;
+            mem_ad_o    <= 0;
+            pc          <= 0;
+            fsm_stage   <= 0;
+        end else begin
+            case (fsm_stage)
+                FSM_STAGE_REQUEST: begin
+                    mem_ad_o  <= pc;
+                    mem_req_o <= 1;
+                    fsm_stage <= FSM_STAGE_WAIT;
+                end
+                FSM_STAGE_WAIT: begin
+                    if (memop_done_i) begin
+                        mem_req_o  <= 0;
+                        pc         <=  pc + 4;
+                        fsm_stage  <= FSM_STAGE_REQUEST;
+                    end
+                end
+            endcase
+        end
+    end
+endmodule
diff --git a/rtl/cpu/cpu_lockdom.sv b/rtl/cpu/cpu_lockdom.sv
index 5ed843b..e370360 100644
--- a/rtl/cpu/cpu_lockdom.sv
+++ b/rtl/cpu/cpu_lockdom.sv
@@ -19,7 +19,7 @@ module cpu_lockdom (
     output AriFrame mb_r_tap_o
 );
     logic imc_write_en = 0;
-    logic imc_req = 0;
+    logic imc_req;
     logic imc_op_done;
     logic [PMA_XLEN-1:0] imc_ad;
     logic [63:0] imc_data;
@@ -35,4 +35,12 @@ module cpu_lockdom (
         .mb_r_tap_o(mb_r_tap_o),
         .op_done_o(imc_op_done)
     );
+
+    cpu_core master (
+        .clk_i(clk_i),
+        .reset_i(reset_i),
+        .imc_op_done_i(imc_op_done),
+        .imc_req_o(imc_req),
+        .imc_ad_o(imc_ad)
+    );
 endmodule