diff options
| author | Ian M. <ian@aptel.org> | 2026-09-25 22:17:07 +0000 |
|---|---|---|
| committer | Ian M. <ian@aptel.org> | 2026-09-25 22:17:07 +0000 |
| commit | 180e410baa026276bd79c202ac9d731f07681a00 (patch) | |
| tree | 8eb9df6f0fe2c38ceace9b5dc1f1965176900cfb /rtl/soc.sv | |
initial commit
Signed-off-by: Ian M. <ian@aptel.org>
Diffstat (limited to 'rtl/soc.sv')
| -rw-r--r-- | rtl/soc.sv | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/rtl/soc.sv b/rtl/soc.sv new file mode 100644 index 0000000..fb33093 --- /dev/null +++ b/rtl/soc.sv @@ -0,0 +1,39 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// The AT-LI02 System-on-Chip (SoC) package +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @pwr_good_o: Power good indicator output +// +module soc ( + input wire refclk_i, + input wire reset_ni, + + output logic pwr_good_o +); + logic dclk; + logic gclk; + logic greset; + + // Platform uncore + uncore uc ( + .refclk_i(refclk_i), + .reset_ni(reset_ni), + .dclk_o(dclk), + .gclk_o(gclk), + .greset_o(greset) + ); + + always_ff @(posedge dclk) begin + if (greset) begin + pwr_good_o <= 0; + end else begin + pwr_good_o <= 1; + end + end +endmodule |
