initial commit

Signed-off-by: Ian M. <ian@aptel.org>

1 files changed, 43 insertions, 0 deletions

diff --git a/rtl/uncore/clkgen.sv b/rtl/uncore/clkgen.sv
new file mode 100644
index 0000000..0c7ff71
--- /dev/null
+++ b/rtl/uncore/clkgen.sv
@@ -0,0 +1,43 @@
+//
+// Copyright (c) 2026, Apollo Telephone Laboratories.
+// Provided under the BSD-3 clause.
+//
+
+//
+// Uncore clock generator
+//
+// @refclk_i:       Reference clock input from on-board VCO
+// @reset_ni:       Active-low reset input
+// @clk_en_i:       Active-high clock enable input
+// @dclk_o:         Derieved clock output
+// @gclk_o:         Gated global clock output
+// @pll_locked_o:   PLL locked indicator output
+//
+module clkgen (
+    input wire refclk_i,
+    input wire reset_ni,
+    input wire clk_en_i,
+
+    output logic dclk_o,
+    output logic gclk_o,
+    output logic pll_locked_o
+);
+    logic clk_en;
+    logic dclk;
+
+    // TODO: Handle real silicon
+`ifdef _SIM
+    assign dclk = refclk_i;
+    assign pll_locked_o = 1;
+`endif
+
+    // ICG cell
+    always_latch begin
+        if (!dclk) begin
+            clk_en = clk_en_i;
+        end
+    end
+
+    assign gclk_o = dclk & clk_en;
+    assign dclk_o = dclk;
+endmodule