uncore: clkgen: Add 300 MHz phased locked loop

Signed-off-by: Ian M. <ian@aptel.org>

1 files changed, 7 insertions, 0 deletions

diff --git a/rtl/uncore/clkgen.sv b/rtl/uncore/clkgen.sv
index 0c7ff71..9390e53 100644
--- a/rtl/uncore/clkgen.sv
+++ b/rtl/uncore/clkgen.sv
@@ -29,6 +29,13 @@ module clkgen (
 `ifdef _SIM
     assign dclk = refclk_i;
     assign pll_locked_o = 1;
+`else
+    gpll pll (
+        .reset(~reset_ni),
+        .clk_in1(refclk_i),
+        .clk_out1(dclk),
+        .locked(pll_locked_o)
+    );
 `endif
 
     // ICG cell