diff options
| author | Ian M. <ian@aptel.org> | 2026-09-25 22:17:07 +0000 |
|---|---|---|
| committer | Ian M. <ian@aptel.org> | 2026-09-25 22:17:07 +0000 |
| commit | 180e410baa026276bd79c202ac9d731f07681a00 (patch) | |
| tree | 8eb9df6f0fe2c38ceace9b5dc1f1965176900cfb /rtl/uncore/north_bridge.sv | |
initial commit
Signed-off-by: Ian M. <ian@aptel.org>
Diffstat (limited to 'rtl/uncore/north_bridge.sv')
| -rw-r--r-- | rtl/uncore/north_bridge.sv | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/rtl/uncore/north_bridge.sv b/rtl/uncore/north_bridge.sv new file mode 100644 index 0000000..f2aa285 --- /dev/null +++ b/rtl/uncore/north_bridge.sv @@ -0,0 +1,48 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// The AT-LI02 uncore north-bridge +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @dclk_o: Derieved clock output +// @gclk_o: Gated global clock output +// @greset_o: Global reset output +// +module north_bridge ( + input wire refclk_i, + input wire reset_ni, + + output logic dclk_o, + output logic gclk_o, + output logic greset_o +); + logic clk_en = 1; + logic dclk; + logic gclk; + logic pll_locked; + logic greset; + + // Clock domain 0 + clkgen clkdom0 ( + .refclk_i(refclk_i), + .reset_ni(reset_ni), + .clk_en_i(clk_en), + .dclk_o(dclk), + .gclk_o(gclk), + .pll_locked_o(pll_locked) + ); + + // Reset bridge + always_ff @(posedge dclk) begin + greset <= ~reset_ni | ~pll_locked; + end + + // Continuous assignments + assign dclk_o = dclk; + assign gclk_o = gclk; + assign greset_o = greset; +endmodule |
