bus: ari: Implement ARI interconnect groundwork

Signed-off-by: Ian M. <ian@aptel.org>

1 files changed, 11 insertions, 0 deletions

diff --git a/rtl/uncore/uncore.sv b/rtl/uncore/uncore.sv
index f34577f..11ed4df 100644
--- a/rtl/uncore/uncore.sv
+++ b/rtl/uncore/uncore.sv
@@ -3,11 +3,14 @@
 // Provided under the BSD-3 clause.
 //
 
+`include "bus/ari.svh"
+
 //
 // AT-LI02 uncore
 //
 // @refclk_i:   Reference clock input from on-board VCO
 // @reset_ni:   Active-low reset input
+// @mb_r_tap_i: Mainbus request taps input
 // @dclk_o:     Derieved clock output
 // @gclk_o:     Global clock output
 // @greset_o:   Active-high global reset output
@@ -15,6 +18,7 @@
 module uncore (
     input wire refclk_i,
     input wire reset_ni,
+    input AriFrame mb_r_tap_i[0:ARI_SEGMENT_COUNT-1],
 
     output logic dclk_o,
     output logic gclk_o,
@@ -33,6 +37,13 @@ module uncore (
         .greset_o(greset)
     );
 
+    // Platform mainbus
+    ari_mainbus mainbus (
+        .clk_i(gclk),
+        .reset_i(greset),
+        .r_tap_i(mb_r_tap_i)
+    );
+
     // Continuous assignments
     assign greset_o = greset;
     assign dclk_o   = dclk;