diff options
| -rw-r--r-- | .gitignore | 2 | ||||
| -rw-r--r-- | Makefile | 12 | ||||
| -rw-r--r-- | rtl/soc.sv | 39 | ||||
| -rw-r--r-- | rtl/uncore/clkgen.sv | 43 | ||||
| -rw-r--r-- | rtl/uncore/north_bridge.sv | 48 | ||||
| -rw-r--r-- | rtl/uncore/uncore.sv | 40 | ||||
| -rw-r--r-- | tb/testbench.sv | 33 |
7 files changed, 217 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..799b71c --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +*.vcd +/soc diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..fde28a3 --- /dev/null +++ b/Makefile @@ -0,0 +1,12 @@ +# +# Copyright (c) 2026, Apollo Telephone Laboratories. +# Provided under the BSD-3 clause. +# + +SV_FILES = $(shell find rtl -name "*.sv") +SV_FLAGS = -D_SIM -g2012 -Irtl/inc + +.PHONY: all +all: + iverilog $(SV_FILES) tb/testbench.sv $(SV_FLAGS) -o soc + ./soc diff --git a/rtl/soc.sv b/rtl/soc.sv new file mode 100644 index 0000000..fb33093 --- /dev/null +++ b/rtl/soc.sv @@ -0,0 +1,39 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// The AT-LI02 System-on-Chip (SoC) package +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @pwr_good_o: Power good indicator output +// +module soc ( + input wire refclk_i, + input wire reset_ni, + + output logic pwr_good_o +); + logic dclk; + logic gclk; + logic greset; + + // Platform uncore + uncore uc ( + .refclk_i(refclk_i), + .reset_ni(reset_ni), + .dclk_o(dclk), + .gclk_o(gclk), + .greset_o(greset) + ); + + always_ff @(posedge dclk) begin + if (greset) begin + pwr_good_o <= 0; + end else begin + pwr_good_o <= 1; + end + end +endmodule diff --git a/rtl/uncore/clkgen.sv b/rtl/uncore/clkgen.sv new file mode 100644 index 0000000..0c7ff71 --- /dev/null +++ b/rtl/uncore/clkgen.sv @@ -0,0 +1,43 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// Uncore clock generator +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @clk_en_i: Active-high clock enable input +// @dclk_o: Derieved clock output +// @gclk_o: Gated global clock output +// @pll_locked_o: PLL locked indicator output +// +module clkgen ( + input wire refclk_i, + input wire reset_ni, + input wire clk_en_i, + + output logic dclk_o, + output logic gclk_o, + output logic pll_locked_o +); + logic clk_en; + logic dclk; + + // TODO: Handle real silicon +`ifdef _SIM + assign dclk = refclk_i; + assign pll_locked_o = 1; +`endif + + // ICG cell + always_latch begin + if (!dclk) begin + clk_en = clk_en_i; + end + end + + assign gclk_o = dclk & clk_en; + assign dclk_o = dclk; +endmodule diff --git a/rtl/uncore/north_bridge.sv b/rtl/uncore/north_bridge.sv new file mode 100644 index 0000000..f2aa285 --- /dev/null +++ b/rtl/uncore/north_bridge.sv @@ -0,0 +1,48 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// The AT-LI02 uncore north-bridge +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @dclk_o: Derieved clock output +// @gclk_o: Gated global clock output +// @greset_o: Global reset output +// +module north_bridge ( + input wire refclk_i, + input wire reset_ni, + + output logic dclk_o, + output logic gclk_o, + output logic greset_o +); + logic clk_en = 1; + logic dclk; + logic gclk; + logic pll_locked; + logic greset; + + // Clock domain 0 + clkgen clkdom0 ( + .refclk_i(refclk_i), + .reset_ni(reset_ni), + .clk_en_i(clk_en), + .dclk_o(dclk), + .gclk_o(gclk), + .pll_locked_o(pll_locked) + ); + + // Reset bridge + always_ff @(posedge dclk) begin + greset <= ~reset_ni | ~pll_locked; + end + + // Continuous assignments + assign dclk_o = dclk; + assign gclk_o = gclk; + assign greset_o = greset; +endmodule diff --git a/rtl/uncore/uncore.sv b/rtl/uncore/uncore.sv new file mode 100644 index 0000000..f34577f --- /dev/null +++ b/rtl/uncore/uncore.sv @@ -0,0 +1,40 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// AT-LI02 uncore +// +// @refclk_i: Reference clock input from on-board VCO +// @reset_ni: Active-low reset input +// @dclk_o: Derieved clock output +// @gclk_o: Global clock output +// @greset_o: Active-high global reset output +// +module uncore ( + input wire refclk_i, + input wire reset_ni, + + output logic dclk_o, + output logic gclk_o, + output logic greset_o +); + logic dclk; + logic gclk; + logic greset; + + // North bridge + north_bridge uncore_north ( + .refclk_i(refclk_i), + .reset_ni(reset_ni), + .dclk_o(dclk), + .gclk_o(gclk), + .greset_o(greset) + ); + + // Continuous assignments + assign greset_o = greset; + assign dclk_o = dclk; + assign gclk_o = gclk; +endmodule diff --git a/tb/testbench.sv b/tb/testbench.sv new file mode 100644 index 0000000..d290fde --- /dev/null +++ b/tb/testbench.sv @@ -0,0 +1,33 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`timescale 1ns / 1ps + +module testbench; + logic clk = 0; + logic reset_n = 1; + logic pwr_good; + + soc soc_dut ( + .refclk_i(clk), + .reset_ni(reset_n), + .pwr_good_o(pwr_good) + ); + + always #1 clk = ~clk; + initial begin + // Assert chip-wide reset + #1 reset_n = 0; + #4 reset_n = 1; + + #300; + $finish; + end + + initial begin + $dumpfile("soc.vcd"); + $dumpvars(0, testbench); + end +endmodule |