diff options
Diffstat (limited to 'rtl/cpu')
| -rw-r--r-- | rtl/cpu/cpu_appdom.sv | 25 | ||||
| -rw-r--r-- | rtl/cpu/cpu_imc.sv | 79 | ||||
| -rw-r--r-- | rtl/cpu/cpu_lockdom.sv | 37 |
3 files changed, 141 insertions, 0 deletions
diff --git a/rtl/cpu/cpu_appdom.sv b/rtl/cpu/cpu_appdom.sv new file mode 100644 index 0000000..f1e67bb --- /dev/null +++ b/rtl/cpu/cpu_appdom.sv @@ -0,0 +1,25 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +// +// Represents a processor application domain +// +// @clk_i: Input clock +// @reset_i: Reset input +// @mb_r_tap<n>_o: Mainbus request tap output +// +module cpu_appdom ( + input wire clk_i, + input wire reset_i, + + output AriFrame mb_r_tap0_o +); + // Lockstep domain 0 + cpu_lockdom lockdom0 ( + .clk_i(clk_i), + .reset_i(reset_i), + .mb_r_tap_o(mb_r_tap0_o) + ); +endmodule diff --git a/rtl/cpu/cpu_imc.sv b/rtl/cpu/cpu_imc.sv new file mode 100644 index 0000000..2dfca60 --- /dev/null +++ b/rtl/cpu/cpu_imc.sv @@ -0,0 +1,79 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// The integrated memory controller (IMC) is responsible for making +// bus transactions using the address operation tag. +// +module cpu_imc ( + input wire clk_i, + input wire reset_i, + input wire write_en_i, + input wire req_i, + input wire [PMA_XLEN-1:0] ad_i, + input wire [63:0] data_i, + + output AriFrame mb_r_tap_o, + output logic op_done_o +); + parameter FSM_STAGE_REQUEST = 0; + parameter FSM_STAGE_TX_REQ = 1; + parameter FSM_STAGE_WAIT0 = 2; + parameter FSM_STAGE_WAIT1 = 3; + parameter FSM_STAGE_WAIT2 = 4; + parameter FSM_STAGE_WAIT3 = 5; + parameter FSM_STAGE_DONE = 6; + + logic [3:0] fsm_stage; + logic [3:0] seq; + AriAdop adop; + AriFrame frame; + + always_ff @(posedge clk_i) begin + if (reset_i) begin + frame <= 0; + fsm_stage <= 0; + mb_r_tap_o <= 0; + op_done_o <= 0; + seq <= 0; + end else if (req_i || fsm_stage > FSM_STAGE_REQUEST) begin + case (fsm_stage) + FSM_STAGE_REQUEST: begin + frame.tag <= ARI_ADOP; + frame.seq <= seq; + frame.payload <= adop; + fsm_stage <= FSM_STAGE_TX_REQ; + end + FSM_STAGE_TX_REQ: begin + mb_r_tap_o <= frame; + fsm_stage <= FSM_STAGE_WAIT0; + end + + // Four cycle wait period as per the spec + FSM_STAGE_WAIT0: fsm_stage <= FSM_STAGE_WAIT1; + FSM_STAGE_WAIT1: fsm_stage <= FSM_STAGE_WAIT2; + FSM_STAGE_WAIT2: fsm_stage <= FSM_STAGE_WAIT3; + FSM_STAGE_WAIT3: fsm_stage <= FSM_STAGE_DONE; + + FSM_STAGE_DONE: begin + mb_r_tap_o <= 0; + op_done_o <= 1; + if (!req_i) begin + fsm_stage <= FSM_STAGE_REQUEST; + op_done_o <= 0; + end + end + endcase + end + end + + // Continous assignments + assign adop.ad = ad_i; + assign adop.data = write_en_i ? data_i : 0; + assign adop.write_en = write_en_i; + assign adop.reserved = 0; +endmodule diff --git a/rtl/cpu/cpu_lockdom.sv b/rtl/cpu/cpu_lockdom.sv new file mode 100644 index 0000000..81d3d6a --- /dev/null +++ b/rtl/cpu/cpu_lockdom.sv @@ -0,0 +1,37 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// Represents a lockstep domain +// +// @clk_i: Clock input +// @reset_i: +// +module cpu_lockdom ( + input wire clk_i, + input wire reset_i, + + output AriFrame mb_r_tap_o +); + logic imc_write_en = 0; + logic imc_req = 0; + logic imc_op_done; + logic [PMA_XLEN-1:0] imc_ad; + logic [63:0] imc_data; + + // Integrated memory controller + cpu_imc imc ( + .clk_i(clk_i), + .reset_i(reset_i), + .write_en_i(imc_write_en), + .req_i(imc_req), + .ad_i(imc_ad), + .data_i(imc_data), + .mb_r_tap_o(mb_r_tap_o), + .op_done_o(imc_op_done) + ); +endmodule |