diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/bus/ari_framemux.sv | 91 | ||||
| -rw-r--r-- | rtl/bus/ari_mainbus.sv | 26 | ||||
| -rw-r--r-- | rtl/bus/ari_ring.sv | 52 | ||||
| -rw-r--r-- | rtl/bus/ari_segment.sv | 33 | ||||
| -rw-r--r-- | rtl/soc.sv | 15 | ||||
| -rw-r--r-- | rtl/uncore/uncore.sv | 11 |
6 files changed, 228 insertions, 0 deletions
diff --git a/rtl/bus/ari_framemux.sv b/rtl/bus/ari_framemux.sv new file mode 100644 index 0000000..9b76a51 --- /dev/null +++ b/rtl/bus/ari_framemux.sv @@ -0,0 +1,91 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// Represents an ARI segment frame multiplexer +// +// @clk_i: Clock input +// @reset_i: Reset input +// @ingress_i: Ingress frame input +// @tap_i: Tap port input +// @egress_o: Egress frame output +// +module ari_framemux ( + input wire clk_i, + input wire reset_i, + input AriFrame ingress_i, + input AriFrame tap_i, + + output AriFrame egress_o +); + // Multiplexer attributes + parameter MUX_PERIOD = 2; + parameter MUX_N_INPUT = 2; + parameter MUX_N_STATES = (MUX_PERIOD * MUX_N_INPUT); + + // Multiplexer states + parameter MUX_STATE_INGRESS0 = 0; + parameter MUX_STATE_INGRESS1 = 1; + parameter MUX_STATE_TAP0 = 2; + parameter MUX_STATE_TAP1 = 3; + + // TDM selector + logic [2:0] mux_sel; + + // + // Handle reset logic and time division multiplexing for + // frame routing. If there is nothing on the channel that + // is currently being selected, we are to route the other + // channel instead. + // + always_ff @(posedge clk_i) begin + if (reset_i) begin + mux_sel <= 0; + egress_o <= 0; + end else begin + case (mux_sel) + // TDM ingress slice + MUX_STATE_INGRESS0: begin + if (ingress_i == 0) begin + egress_o <= tap_i; + end else begin + egress_o <= ingress_i; + end + end + MUX_STATE_INGRESS1: begin + if (ingress_i == 0) begin + egress_o <= tap_i; + end else begin + egress_o <= ingress_i; + end + end + + // TDM tap slice + MUX_STATE_TAP0: begin + if (tap_i == 0) begin + egress_o <= ingress_i; + end else begin + egress_o <= tap_i; + end + end + MUX_STATE_TAP1: begin + if (tap_i == 0) begin + egress_o <= ingress_i; + end else begin + egress_o <= tap_i; + end + end + endcase + end + + if (!reset_i && mux_sel < MUX_N_STATES) begin + mux_sel <= mux_sel + 1; + end else if (!reset_i && mux_sel >= MUX_N_STATES) begin + mux_sel <= 0; + end + end +endmodule diff --git a/rtl/bus/ari_mainbus.sv b/rtl/bus/ari_mainbus.sv new file mode 100644 index 0000000..225fa03 --- /dev/null +++ b/rtl/bus/ari_mainbus.sv @@ -0,0 +1,26 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// On-chip mainbus +// +// @clk_i: Clock input +// @reset_i: Reset input +// @r_tap_i: Request taps +// +module ari_mainbus ( + input wire clk_i, + input wire reset_i, + input AriFrame r_tap_i[0:ARI_SEGMENT_COUNT-1] +); + // Request ring + ari_ring req_ring ( + .clk_i(clk_i), + .reset_i(reset_i), + .tap_i(r_tap_i) + ); +endmodule diff --git a/rtl/bus/ari_ring.sv b/rtl/bus/ari_ring.sv new file mode 100644 index 0000000..48062c7 --- /dev/null +++ b/rtl/bus/ari_ring.sv @@ -0,0 +1,52 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// Represents a ring of ARI segments which forms a single +// bus channel. +// +// @clk_i: Clock input +// @reset_i: Reset input +// @tap_i: Segment taps +// +module ari_ring ( + input wire clk_i, + input wire reset_i, + input AriFrame tap_i[0:ARI_SEGMENT_COUNT-1] +); + // Segment feeders + AriFrame seg3_feed; + AriFrame seg2_feed; + AriFrame seg1_feed; + + // Segment 0 + ari_segment seg0 ( + .clk_i(clk_i), + .reset_i(reset_i), + .ingress_i(seg3_feed), + .tap_i(tap_i[0]), + .egress_o(seg1_feed) + ); + + // Segment 1 + ari_segment seg1 ( + .clk_i(clk_i), + .reset_i(reset_i), + .ingress_i(seg1_feed), + .tap_i(tap_i[1]), + .egress_o(seg2_feed) + ); + + // Segment 2 + ari_segment seg2 ( + .clk_i(clk_i), + .reset_i(reset_i), + .ingress_i(seg2_feed), + .tap_i(tap_i[2]), + .egress_o(seg3_feed) + ); +endmodule diff --git a/rtl/bus/ari_segment.sv b/rtl/bus/ari_segment.sv new file mode 100644 index 0000000..0523101 --- /dev/null +++ b/rtl/bus/ari_segment.sv @@ -0,0 +1,33 @@ +// +// Copyright (c) 2026, Apollo Telephone Laboratories. +// Provided under the BSD-3 clause. +// + +`include "bus/ari.svh" + +// +// Represents an ARI segment that routes bus data +// +// @clk_i: Clock input +// @reset_i: Reset input +// @ingress_i: Ingress frame input +// @tap_i: Tap port input +// @egress_o: Egress frame output +// +module ari_segment ( + input wire clk_i, + input wire reset_i, + input AriFrame ingress_i, + input AriFrame tap_i, + + output AriFrame egress_o +); + // Frame multiplexer + ari_framemux fmux ( + .clk_i(clk_i), + .reset_i(reset_i), + .ingress_i(ingress_i), + .tap_i(tap_i), + .egress_o(egress_o) + ); +endmodule @@ -3,6 +3,8 @@ // Provided under the BSD-3 clause. // +`include "bus/ari.svh" + // // The AT-LI02 System-on-Chip (SoC) package // @@ -16,19 +18,32 @@ module soc ( output logic pwr_good_o ); + AriFrame mb_r_tap[0:ARI_SEGMENT_COUNT-1]; logic dclk; logic gclk; logic greset; + genvar i; // Platform uncore uncore uc ( .refclk_i(refclk_i), .reset_ni(reset_ni), + .mb_r_tap_i(mb_r_tap), .dclk_o(dclk), .gclk_o(gclk), .greset_o(greset) ); + // + // Zero out currently unused segment taps so that there + // is no garbage put onto the bus. + // + generate + for (i = 0; i < ARI_SEGMENT_COUNT; i = i + 1) begin : bus_rst + assign mb_r_tap[i] = 0; + end + endgenerate + always_ff @(posedge dclk) begin if (greset) begin pwr_good_o <= 0; diff --git a/rtl/uncore/uncore.sv b/rtl/uncore/uncore.sv index f34577f..11ed4df 100644 --- a/rtl/uncore/uncore.sv +++ b/rtl/uncore/uncore.sv @@ -3,11 +3,14 @@ // Provided under the BSD-3 clause. // +`include "bus/ari.svh" + // // AT-LI02 uncore // // @refclk_i: Reference clock input from on-board VCO // @reset_ni: Active-low reset input +// @mb_r_tap_i: Mainbus request taps input // @dclk_o: Derieved clock output // @gclk_o: Global clock output // @greset_o: Active-high global reset output @@ -15,6 +18,7 @@ module uncore ( input wire refclk_i, input wire reset_ni, + input AriFrame mb_r_tap_i[0:ARI_SEGMENT_COUNT-1], output logic dclk_o, output logic gclk_o, @@ -33,6 +37,13 @@ module uncore ( .greset_o(greset) ); + // Platform mainbus + ari_mainbus mainbus ( + .clk_i(gclk), + .reset_i(greset), + .r_tap_i(mb_r_tap_i) + ); + // Continuous assignments assign greset_o = greset; assign dclk_o = dclk; |