From 826f773af17ee09a2bb03fe184aa8967b0083df3 Mon Sep 17 00:00:00 2001
From: "Ian M." <ian@aptel.org>
Date: Fri, 25 Sep 2026 22:39:40 +0000
Subject: uncore: clkgen: Add 300 MHz phased locked loop

Signed-off-by: Ian M. <ian@aptel.org>
---
 rtl/uncore/clkgen.sv | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/rtl/uncore/clkgen.sv b/rtl/uncore/clkgen.sv
index 0c7ff71..9390e53 100644
--- a/rtl/uncore/clkgen.sv
+++ b/rtl/uncore/clkgen.sv
@@ -29,6 +29,13 @@ module clkgen (
 `ifdef _SIM
     assign dclk = refclk_i;
     assign pll_locked_o = 1;
+`else
+    gpll pll (
+        .reset(~reset_ni),
+        .clk_in1(refclk_i),
+        .clk_out1(dclk),
+        .locked(pll_locked_o)
+    );
 `endif
 
     // ICG cell
-- 
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