//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

`include "bus/ari.svh"

//
// Represents a CPU fetch
//
module cpu_fetch (
    input wire clk_i,
    input wire reset_i,
    input wire memop_done_i,

    output logic mem_req_o,
    output logic [PMA_XLEN-1:0] mem_ad_o
);
    parameter FSM_STAGE_REQUEST   = 0;
    parameter FSM_STAGE_WAIT      = 1;

    logic [63:0] pc;
    logic [2:0] fsm_stage;

    always_ff @(posedge clk_i) begin
        if (reset_i) begin
            mem_req_o   <= 0;
            mem_ad_o    <= 0;
            pc          <= 0;
            fsm_stage   <= 0;
        end else begin
            case (fsm_stage)
                FSM_STAGE_REQUEST: begin
                    mem_ad_o  <= pc;
                    mem_req_o <= 1;
                    fsm_stage <= FSM_STAGE_WAIT;
                end
                FSM_STAGE_WAIT: begin
                    if (memop_done_i) begin
                        mem_req_o  <= 0;
                        pc         <=  pc + 4;
                        fsm_stage  <= FSM_STAGE_REQUEST;
                    end
                end
            endcase
        end
    end
endmodule