//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

`include "bus/ari.svh"

//
// Represents a lockstep domain
//
// @clk_i:          Clock input
// @reset_i:        Reset input
// @mb_r_tap_o:     Mainbus request tap output
//
module cpu_lockdom (
    input wire clk_i,
    input wire reset_i,

    output AriFrame mb_r_tap_o
);
    logic imc_write_en = 0;
    logic imc_req = 0;
    logic imc_op_done;
    logic [PMA_XLEN-1:0] imc_ad;
    logic [63:0] imc_data;

    // Integrated memory controller
    cpu_imc imc (
        .clk_i(clk_i),
        .reset_i(reset_i),
        .write_en_i(imc_write_en),
        .req_i(imc_req),
        .ad_i(imc_ad),
        .data_i(imc_data),
        .mb_r_tap_o(mb_r_tap_o),
        .op_done_o(imc_op_done)
    );
endmodule