rtl/soc.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

//
// The AT-LI02 System-on-Chip (SoC) package
//
// @refclk_i:   Reference clock input from on-board VCO
// @reset_ni:   Active-low reset input
// @pwr_good_o: Power good indicator output
//
module soc (
    input wire refclk_i,
    input wire reset_ni,

    output logic pwr_good_o
);
    logic dclk;
    logic gclk;
    logic greset;

    // Platform uncore
    uncore uc (
        .refclk_i(refclk_i),
        .reset_ni(reset_ni),
        .dclk_o(dclk),
        .gclk_o(gclk),
        .greset_o(greset)
    );

    always_ff @(posedge dclk) begin
        if (greset) begin
            pwr_good_o  <= 0;
        end else begin
            pwr_good_o  <= 1;
        end
    end
endmodule