rtl/soc.sv


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//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

`include "bus/ari.svh"

//
// The AT-LI02 System-on-Chip (SoC) package
//
// @refclk_i:   Reference clock input from on-board VCO
// @reset_ni:   Active-low reset input
// @pwr_good_o: Power good indicator output
//
module soc (
    input wire refclk_i,
    input wire reset_ni,

    output logic pwr_good_o
);
    AriFrame mb_r_tap[0:ARI_SEGMENT_COUNT-1];
    logic dclk;
    logic gclk;
    logic greset;
    genvar i;

    // Platform uncore
    uncore uc (
        .refclk_i(refclk_i),
        .reset_ni(reset_ni),
        .mb_r_tap_i(mb_r_tap),
        .dclk_o(dclk),
        .gclk_o(gclk),
        .greset_o(greset)
    );

    //
    // Zero out currently unused segment taps so that there
    // is no garbage put onto the bus.
    //
    generate
        for (i = 0; i < ARI_SEGMENT_COUNT; i = i + 1) begin : bus_rst
            assign mb_r_tap[i] = 0;
        end
    endgenerate

    always_ff @(posedge dclk) begin
        if (greset) begin
            pwr_good_o  <= 0;
        end else begin
            pwr_good_o  <= 1;
        end
    end
endmodule