rtl/uncore/uncore.sv


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//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

`include "bus/ari.svh"

//
// AT-LI02 uncore
//
// @refclk_i:   Reference clock input from on-board VCO
// @reset_ni:   Active-low reset input
// @mb_r_tap_i: Mainbus request taps input
// @dclk_o:     Derieved clock output
// @gclk_o:     Global clock output
// @greset_o:   Active-high global reset output
//
module uncore (
    input wire refclk_i,
    input wire reset_ni,
    input AriFrame mb_r_tap_i[0:ARI_SEGMENT_COUNT-1],

    output logic dclk_o,
    output logic gclk_o,
    output logic greset_o
);
    logic dclk;
    logic gclk;
    logic greset;

    // North bridge
    north_bridge uncore_north (
        .refclk_i(refclk_i),
        .reset_ni(reset_ni),
        .dclk_o(dclk),
        .gclk_o(gclk),
        .greset_o(greset)
    );

    // Platform mainbus
    ari_mainbus mainbus (
        .clk_i(gclk),
        .reset_i(greset),
        .r_tap_i(mb_r_tap_i)
    );

    // Continuous assignments
    assign greset_o = greset;
    assign dclk_o   = dclk;
    assign gclk_o   = gclk;
endmodule