tb/testbench.sv


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

//
// Copyright (c) 2026, Apollo Telephone Laboratories.
// Provided under the BSD-3 clause.
//

`timescale 1ns / 1ps

module testbench;
    logic clk = 0;
    logic reset_n = 1;
    logic pwr_good;

    soc soc_dut (
        .refclk_i(clk),
        .reset_ni(reset_n),
        .pwr_good_o(pwr_good)
    );

    always #1 clk = ~clk;
    initial begin
        // Assert chip-wide reset
        #1 reset_n = 0;
        #4 reset_n = 1;

        #300;
        $finish;
    end

    initial begin
        $dumpfile("soc.vcd");
        $dumpvars(0, testbench);
    end
endmodule